[llvm] r329347 - [X86] Add LEAVE instruction to the scheduler models using the same data as LEAVE64. Make LEAVE/LEAVE64 more correct on Sandy Bridge.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 5 14:16:26 PDT 2018
Author: ctopper
Date: Thu Apr 5 14:16:26 2018
New Revision: 329347
URL: http://llvm.org/viewvc/llvm-project?rev=329347&view=rev
Log:
[X86] Add LEAVE instruction to the scheduler models using the same data as LEAVE64. Make LEAVE/LEAVE64 more correct on Sandy Bridge.
This is the 32-bit mode version of LEAVE64. It should be at least somewhat similar to LEAVE64.
The Sandy Bridge version was missing a load port use.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll
llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=329347&r1=329346&r2=329347&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Thu Apr 5 14:16:26 2018
@@ -1789,11 +1789,8 @@ def BWWriteResGroup80 : SchedWriteRes<[B
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[BWWriteResGroup80], (instregex "LEAVE64",
- "SCASB",
- "SCASL",
- "SCASQ",
- "SCASW")>;
+def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
+ SCASB, SCASL, SCASQ, SCASW)>;
def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
let Latency = 7;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=329347&r1=329346&r2=329347&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Thu Apr 5 14:16:26 2018
@@ -1675,11 +1675,8 @@ def HWWriteResGroup37 : SchedWriteRes<[H
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[HWWriteResGroup37], (instregex "LEAVE64",
- "SCASB",
- "SCASL",
- "SCASQ",
- "SCASW")>;
+def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64,
+ SCASB, SCASL, SCASQ, SCASW)>;
def HWWriteResGroup38 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
let Latency = 8;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=329347&r1=329346&r2=329347&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Thu Apr 5 14:16:26 2018
@@ -794,8 +794,14 @@ def SBWriteResGroup25 : SchedWriteRes<[S
let NumMicroOps = 3;
let ResourceCycles = [3];
}
-def: InstRW<[SBWriteResGroup25], (instregex "LEAVE64",
- "XADD(8|16|32|64)rr")>;
+def: InstRW<[SBWriteResGroup25], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr)>;
+
+def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> {
+ let Latency = 7;
+ let NumMicroOps = 3;
+ let ResourceCycles = [1,2];
+}
+def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>;
def SBWriteResGroup25_2 : SchedWriteRes<[SBPort5,SBPort05]> {
let Latency = 3;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=329347&r1=329346&r2=329347&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Thu Apr 5 14:16:26 2018
@@ -1779,11 +1779,8 @@ def SKLWriteResGroup94 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKLWriteResGroup94], (instregex "LEAVE64",
- "SCASB",
- "SCASL",
- "SCASQ",
- "SCASW")>;
+def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
+ SCASB, SCASL, SCASQ, SCASW)>;
def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
let Latency = 7;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=329347&r1=329346&r2=329347&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Thu Apr 5 14:16:26 2018
@@ -3709,11 +3709,8 @@ def SKXWriteResGroup99 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKXWriteResGroup99], (instregex "LEAVE64",
- "SCASB",
- "SCASL",
- "SCASQ",
- "SCASW")>;
+def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
+ SCASB, SCASL, SCASQ, SCASW)>;
def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
let Latency = 7;
Modified: llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll?rev=329347&r1=329346&r2=329347&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/schedule-x86_32.ll Thu Apr 5 14:16:26 2018
@@ -1380,35 +1380,35 @@ define void @test_leave() optsize {
; SANDY-LABEL: test_leave:
; SANDY: # %bb.0:
; SANDY-NEXT: #APP
-; SANDY-NEXT: leave # sched: [1:0.33]
+; SANDY-NEXT: leave # sched: [7:0.67]
; SANDY-NEXT: #NO_APP
; SANDY-NEXT: retl # sched: [5:1.00]
;
; HASWELL-LABEL: test_leave:
; HASWELL: # %bb.0:
; HASWELL-NEXT: #APP
-; HASWELL-NEXT: leave # sched: [1:0.25]
+; HASWELL-NEXT: leave # sched: [7:0.50]
; HASWELL-NEXT: #NO_APP
; HASWELL-NEXT: retl # sched: [7:1.00]
;
; BROADWELL-LABEL: test_leave:
; BROADWELL: # %bb.0:
; BROADWELL-NEXT: #APP
-; BROADWELL-NEXT: leave # sched: [1:0.25]
+; BROADWELL-NEXT: leave # sched: [7:0.50]
; BROADWELL-NEXT: #NO_APP
; BROADWELL-NEXT: retl # sched: [6:0.50]
;
; SKYLAKE-LABEL: test_leave:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: #APP
-; SKYLAKE-NEXT: leave # sched: [1:0.25]
+; SKYLAKE-NEXT: leave # sched: [7:0.50]
; SKYLAKE-NEXT: #NO_APP
; SKYLAKE-NEXT: retl # sched: [6:0.50]
;
; SKX-LABEL: test_leave:
; SKX: # %bb.0:
; SKX-NEXT: #APP
-; SKX-NEXT: leave # sched: [1:0.25]
+; SKX-NEXT: leave # sched: [7:0.50]
; SKX-NEXT: #NO_APP
; SKX-NEXT: retl # sched: [6:0.50]
;
Modified: llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll?rev=329347&r1=329346&r2=329347&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll Thu Apr 5 14:16:26 2018
@@ -7385,7 +7385,7 @@ define void @test_leave() optsize {
; GENERIC-LABEL: test_leave:
; GENERIC: # %bb.0:
; GENERIC-NEXT: #APP
-; GENERIC-NEXT: leave # sched: [3:1.00]
+; GENERIC-NEXT: leave # sched: [7:0.67]
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -7406,7 +7406,7 @@ define void @test_leave() optsize {
; SANDY-LABEL: test_leave:
; SANDY: # %bb.0:
; SANDY-NEXT: #APP
-; SANDY-NEXT: leave # sched: [3:1.00]
+; SANDY-NEXT: leave # sched: [7:0.67]
; SANDY-NEXT: #NO_APP
; SANDY-NEXT: retq # sched: [1:1.00]
;
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