[PATCH] D45230: [Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision

[Lei Huang via Phabricator via llvm-commits]

lei added inline comments.


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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:3121
             (f32 (DFLOADf32 ixaddr:$src))>;
+
+  // Convert (Un)Signed DWord in memory -> QP
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nemanjai wrote:
> I just realized that we should also add patterns for converting an extracted vector value to `f128` because it will currently do `mfvsrd -> mtvsrd -> xscv[us]dqp` which is obviously redundant.
> We will also need patterns for extending loads from byte, halfword and word.
Will post patterns for extending these in a separate patch.


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Comment at: test/CodeGen/PowerPC/f128-conv.ll:3
+; RUN:   -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+ at mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
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nemanjai wrote:
> Please add test cases that convert from smaller integer types as well (byte, halfword and word).
will be done in a separate patch


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Comment at: test/CodeGen/PowerPC/f128-conv.ll:22
+; Function Attrs: norecurse nounwind
+define void @sdwConv2qp_02(fp128* nocapture %a) {
+entry:
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nemanjai wrote:
> Please also add a version of the test where the integer value is passed as a parameter by pointer (for both the signed and unsigned conversions).
okay


https://reviews.llvm.org/D45230