[PATCH] D45181: [RISCV WIP] Add diff relocation support for RISC-V

[Ana Pazos via Phabricator via llvm-commits]

apazos added inline comments.


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Comment at: include/llvm/MC/MCFixup.h:48
+  FK_Data_Add_8, ///< A one-byte add fixup.
+  FK_Data_Sub_1, ///< A eight-byte sub fixup.
+  FK_Data_Sub_2, ///< A two-byte sub fixup.
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Comments need to be updated:
FK_Data_Add_8 -> A eight byte..
FK_Data_Sub_1 -> A one-byte..



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Comment at: lib/MC/MCAssembler.cpp:686
+      // backend has indiciated can be resolved at link time. Split up the fixup
+      // into two relocations, one for the add, and one for the addition, and
+      // emit both of these. The constant will be associated with the add half
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Comment update:
 one for the add, and one for the addition, ->  one for the add, and one for the sub,


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Comment at: lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:39
 
+  bool supportsEmittingDiffExpressions() const override { return true; }
+
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Should this setting be conditional on  the relax flag?
The relax flag is being introduced in https://reviews.llvm.org/D44888



Repository:
  rL LLVM

https://reviews.llvm.org/D45181