[llvm] r329243 - [MIR-Canon] Adding support for multi-def -> user distance reduction.
Puyan Lotfi via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 4 17:08:15 PDT 2018
Author: zer0
Date: Wed Apr 4 17:08:15 2018
New Revision: 329243
URL: http://llvm.org/viewvc/llvm-project?rev=329243&view=rev
Log:
[MIR-Canon] Adding support for multi-def -> user distance reduction.
Added:
llvm/trunk/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
Modified:
llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
Modified: llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp?rev=329243&r1=329242&r2=329243&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp Wed Apr 4 17:08:15 2018
@@ -189,6 +189,7 @@ static bool rescheduleCanonically(unsign
Instructions.push_back(&MI);
}
+ std::map<MachineInstr *, std::vector<MachineInstr *>> MultiUsers;
std::vector<MachineInstr *> PseudoIdempotentInstructions;
std::vector<unsigned> PhysRegDefs;
for (auto *II : Instructions) {
@@ -297,10 +298,26 @@ static bool rescheduleCanonically(unsign
UseI->dump();
});
+ MultiUsers[UseToBringDefCloserTo].push_back(Def);
Changed = true;
MBB->splice(UseI, MBB, DefI);
}
+ // Sort the defs for users of multiple defs lexographically.
+ for (const auto &E : MultiUsers) {
+
+ auto UseI =
+ std::find_if(MBB->instr_begin(), MBB->instr_end(),
+ [&](MachineInstr &MI) -> bool { return &MI == E.first; });
+
+ if (UseI == MBB->instr_end())
+ continue;
+
+ DEBUG(dbgs() << "Rescheduling Multi-Use Instructions Lexographically.";);
+ Changed |= rescheduleLexographically(
+ E.second, MBB, [&]() -> MachineBasicBlock::iterator { return UseI; });
+ }
+
PseudoIdempotentInstCount = PseudoIdempotentInstructions.size();
DEBUG(dbgs() << "Rescheduling Idempotent Instructions Lexographically.";);
Changed |= rescheduleLexographically(
Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir?rev=329243&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir Wed Apr 4 17:08:15 2018
@@ -0,0 +1,32 @@
+# RUN: llc -o - -march=amdgcn -run-pass mir-canonicalizer -x mir %s | FileCheck %s
+
+# CHECK: %1363:vgpr_32 = COPY %4354
+# CHECK: %1368:vgpr_32 = COPY %4355
+# CHECK: %1369:vgpr_32 = COPY %1372
+# CHECK: %1370:vgpr_32 = COPY %1373
+# CHECK: REG_SEQUENCE %1368, %subreg.sub0, %1363, %subreg.sub1
+# CHECK: REG_SEQUENCE %1368, %subreg.sub0, %1363, %subreg.sub1, %1369, %subreg.sub2, %1370, %subreg.sub3
+
+...
+---
+name: foo
+body: |
+ bb.0:
+ %10:sreg_32_xm0 = S_MOV_B32 61440
+ %11:sreg_32_xm0 = S_MOV_B32 0
+ %3:vgpr_32 = COPY $vgpr0
+
+ %vreg123_0:vgpr_32 = COPY %3
+ %0:sgpr_64 = COPY $sgpr0_sgpr1
+ %vreg123_1:vgpr_32 = COPY %11
+ %27:vreg_64 = REG_SEQUENCE %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1
+ %4:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 9, 0
+ %vreg123_2:vgpr_32 = COPY %4
+ %5:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 11, 0
+ %vreg123_3:vgpr_32 = COPY %5
+ %16:sgpr_128 = REG_SEQUENCE killed %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1, %vreg123_2, %subreg.sub2, %vreg123_3, %subreg.sub3
+
+ BUFFER_STORE_DWORD_ADDR64 %vreg123_1, %27, killed %16, 0, 0, 0, 0, 0, implicit $exec
+ S_ENDPGM
+
+...
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