[PATCH] D45253: [X86][WAITPKG] WaitPKG instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86InstrInfo.td:2683
+                     "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, XS,
+                    Requires<[HasWAITPKG, In64BitMode]>;
+
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What is the llvm-mc assembler expectation here? As this is defined it means that 64-bit mode assembly must alway use a 64-bit register and 32-bit mode must always use a 32-bit register. The documentation itself mentions being able to use a 16-bit register and that the 0x67 prefix has an effect, but that's not captured here.


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Comment at: lib/Target/X86/X86InstrInfo.td:2701
+                     "tpause\t$src", [(int_x86_tpause64 GR64:$src, EAX, EDX)]>,
+                     PD, Requires<[HasWAITPKG, In64BitMode]>;
+  }
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Again this also has a weird assembler expectation the register size is dependent on the mode.


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Comment at: test/CodeGen/X86/waitpkg-intrinsics-64.ll:14
+  %address.addr = alloca i8*, align 8
+  store i8* %address, i8** %address.addr, align 8
+  %0 = load i8*, i8** %address.addr, align 8
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Can these tests be simplified to not use so many loads and stores? Is this the -O0 clang output? Can we use -O2 output instead.


https://reviews.llvm.org/D45253