[llvm] r329211 - [X86] Separate BSWAP32r and BSWAP64r scheduling data in SandyBridge/Haswell/Broadwell/Skylake scheduler models.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 4 10:54:19 PDT 2018
Author: ctopper
Date: Wed Apr 4 10:54:19 2018
New Revision: 329211
URL: http://llvm.org/viewvc/llvm-project?rev=329211&view=rev
Log:
[X86] Separate BSWAP32r and BSWAP64r scheduling data in SandyBridge/Haswell/Broadwell/Skylake scheduler models.
The BSWAP64r version is 2 uops and BSWAP32r is only 1 uop. The regular expressions also looked for a non-existant BSWAP16r.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=329211&r1=329210&r2=329211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Wed Apr 4 10:54:19 2018
@@ -786,7 +786,14 @@ def BWWriteResGroup19 : SchedWriteRes<[B
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup19], (instregex "BSWAP(16|32|64)r")>;
+def: InstRW<[BWWriteResGroup19], (instrs BSWAP64r)>;
+
+def BWWriteResGroup19_1 : SchedWriteRes<[BWPort15]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[BWWriteResGroup19_1], (instrs BSWAP32r)>;
def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=329211&r1=329210&r2=329211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Wed Apr 4 10:54:19 2018
@@ -1611,7 +1611,14 @@ def HWWriteResGroup34 : SchedWriteRes<[H
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup34], (instregex "BSWAP(16|32|64)r")>;
+def: InstRW<[HWWriteResGroup34], (instrs BSWAP64r)>;
+
+def HWWriteResGroup34_1 : SchedWriteRes<[HWPort15]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[HWWriteResGroup34_1], (instrs BSWAP32r)>;
def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=329211&r1=329210&r2=329211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Wed Apr 4 10:54:19 2018
@@ -621,7 +621,14 @@ def SBWriteResGroup16 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup16], (instregex "BSWAP(16|32|64)r")>;
+def: InstRW<[SBWriteResGroup16], (instrs BSWAP64r)>;
+
+def SBWriteResGroup16_1 : SchedWriteRes<[SBPort1]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SBWriteResGroup16_1], (instrs BSWAP32r)>;
def SBWriteResGroup17 : SchedWriteRes<[SBPort5,SBPort15]> {
let Latency = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=329211&r1=329210&r2=329211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Wed Apr 4 10:54:19 2018
@@ -808,7 +808,14 @@ def SKLWriteResGroup22 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup22], (instregex "BSWAP(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup22], (instrs BSWAP64r)>;
+
+def SKLWriteResGroup22_1 : SchedWriteRes<[SKLPort15]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKLWriteResGroup22_1], (instrs BSWAP32r)>;
def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let Latency = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=329211&r1=329210&r2=329211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Wed Apr 4 10:54:19 2018
@@ -1603,7 +1603,14 @@ def SKXWriteResGroup22 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup22], (instregex "BSWAP(16|32|64)r")>;
+def: InstRW<[SKXWriteResGroup22], (instrs BSWAP64r)>;
+
+def SKXWriteResGroup22_1 : SchedWriteRes<[SKXPort15]> {
+ let Latency = 1;
+ let NumMicroOps = 1;
+ let ResourceCycles = [1];
+}
+def: InstRW<[SKXWriteResGroup22_1], (instrs BSWAP32r)>;
def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
let Latency = 2;
Modified: llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll?rev=329211&r1=329210&r2=329211&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll Wed Apr 4 10:54:19 2018
@@ -2541,7 +2541,7 @@ define i64 @test_bsr64(i64 %a0, i64* %a1
define i32 @test_bswap32(i32 %a0) optsize {
; GENERIC-LABEL: test_bswap32:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: bswapl %edi # sched: [2:1.00]
+; GENERIC-NEXT: bswapl %edi # sched: [1:1.00]
; GENERIC-NEXT: movl %edi, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -2559,31 +2559,31 @@ define i32 @test_bswap32(i32 %a0) optsiz
;
; SANDY-LABEL: test_bswap32:
; SANDY: # %bb.0:
-; SANDY-NEXT: bswapl %edi # sched: [2:1.00]
+; SANDY-NEXT: bswapl %edi # sched: [1:1.00]
; SANDY-NEXT: movl %edi, %eax # sched: [1:0.33]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_bswap32:
; HASWELL: # %bb.0:
-; HASWELL-NEXT: bswapl %edi # sched: [2:0.50]
+; HASWELL-NEXT: bswapl %edi # sched: [1:0.50]
; HASWELL-NEXT: movl %edi, %eax # sched: [1:0.25]
; HASWELL-NEXT: retq # sched: [7:1.00]
;
; BROADWELL-LABEL: test_bswap32:
; BROADWELL: # %bb.0:
-; BROADWELL-NEXT: bswapl %edi # sched: [2:0.50]
+; BROADWELL-NEXT: bswapl %edi # sched: [1:0.50]
; BROADWELL-NEXT: movl %edi, %eax # sched: [1:0.25]
; BROADWELL-NEXT: retq # sched: [7:1.00]
;
; SKYLAKE-LABEL: test_bswap32:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: bswapl %edi # sched: [2:0.50]
+; SKYLAKE-NEXT: bswapl %edi # sched: [1:0.50]
; SKYLAKE-NEXT: movl %edi, %eax # sched: [1:0.25]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_bswap32:
; SKX: # %bb.0:
-; SKX-NEXT: bswapl %edi # sched: [2:0.50]
+; SKX-NEXT: bswapl %edi # sched: [1:0.50]
; SKX-NEXT: movl %edi, %eax # sched: [1:0.25]
; SKX-NEXT: retq # sched: [7:1.00]
;
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