[PATCH] D44905: [mips] Add support for Virtualization ASE

[Simon Dardis via Phabricator via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

This looks mostly ok. The big changes required is that these instructions should go in the relevant base architecture .td, as I don't believe there's enough of them to warrant going into two separate files.



================
Comment at: lib/Target/Mips/MicroMips32r6InstrFormats.td:879
 
+class POOL32A_HYPCALL_FM_MMR6<string instr_asm>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
----------------
The virtualization standard for microMIPS says that the minimum ISA level for that ASE is microMIPS 5.0, so this class definition should go in lib/Target/Mips/MicroMipsInstrFormats.td.

Also, the 'MMR6' suffix should then be 'MM'.


================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:1410
 def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
+def MFGC0_MMR6 : StdMMR6Rel, MFGC0_MMR6_ENC, MFGC0_MMR6_DESC, ISA_MICROMIPS32R6, ASE_VIRT;
+def MTGC0_MMR6 : StdMMR6Rel, MTGC0_MMR6_ENC, MTGC0_MMR6_DESC, ISA_MICROMIPS32R6, ASE_VIRT;
----------------
These lines are overly long.


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Comment at: lib/Target/Mips/Mips64InstrInfo.td:559
+/// Move between CPU and guest coprocessor registers (Virtualization ASE)
+let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
+  def DMFGC0 : MFC3OP<"dmfgc0", GPR64Opnd, COP0Opnd, II_DMFGC0>,
----------------
Drop the 'Predicates = [HasMips64]' for this line as it overrides ISA_MIPS64, ASE_VIRT adjectives.


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Comment at: lib/Target/Mips/Mips64InstrInfo.td:561
+  def DMFGC0 : MFC3OP<"dmfgc0", GPR64Opnd, COP0Opnd, II_DMFGC0>,
+               MFC3OP_FM<0x10, 3, 1>, ISA_MIPS64, ASE_VIRT;
+  def DMTGC0 : MFC3OP<"dmtgc0", COP0Opnd, GPR64Opnd, II_DMTGC0>,
----------------
This should be ISA_MIPS64R5, ASE_VIRT and likewise below.


================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:885
+                      (DMFGC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>,
+                      ISA_MIPS64, ASE_VIRT;
+  def : MipsInstAlias<"dmtgc0 $rt, $rd",
----------------
This should be ISA_MIPS64R5, ASE_VIRT and likewise below.


================
Comment at: lib/Target/Mips/MipsEVAInstrFormats.td:55-62
+// TLBG* from Virtualization ASE
+def OPCODE6_TLBGINV    : OPCODE6<0b001011>;
+def OPCODE6_TLBGINVF   : OPCODE6<0b001100>;
+def OPCODE6_TLBGP      : OPCODE6<0b010000>;
+def OPCODE6_TLBGR      : OPCODE6<0b001001>;
+def OPCODE6_TLBGWI     : OPCODE6<0b001010>;
+def OPCODE6_TLBGWR     : OPCODE6<0b001110>;
----------------
These instructions should go in lib/Target/Mips/MipsInstr{Info, Formats}.td. They are not associated with the EVA ASE.


================
Comment at: lib/Target/Mips/MipsEVAInstrInfo.td:230-239
+  def TLBGINV  : TLBGINV_ENC, TLBGINV_DESC, ISA_MIPS32, ASE_VIRT;
+  def TLBGINVF : TLBGINVF_ENC, TLBGINVF_DESC, ISA_MIPS32, ASE_VIRT;
+  def TLBGP    : TLBGP_ENC, TLBGP_DESC, ISA_MIPS32, ASE_VIRT;
+  def TLBGR    : TLBGR_ENC, TLBGR_DESC, ISA_MIPS32, ASE_VIRT;
+  def TLBGWI   : TLBGWI_ENC, TLBGWI_DESC, ISA_MIPS32, ASE_VIRT;
+  def TLBGWR   : TLBGWR_ENC, TLBGWR_DESC, ISA_MIPS32, ASE_VIRT;
+  def HYPCALL  : MMRel, StdMMR6Rel, HYPCALL_FT<"hypcall">,
----------------
These instructions should be guarded for MIPS32R5, not MIPS32.


================
Comment at: lib/Target/Mips/MipsInstrInfo.td:2333-2336
+  def MFGC0  : MFC3OP<"mfgc0", GPR32Opnd, COP0Opnd, II_MFGC0>,
+               MFC3OP_FM<0x10, 3, 0>, ISA_MIPS32, ASE_VIRT;
+  def MTGC0  : MTC3OP<"mtgc0", COP0Opnd, GPR32Opnd, II_MFGC0>,
+               MFC3OP_FM<0x10, 3, 2>, ISA_MIPS32, ASE_VIRT;
----------------
These instructions should be guarded for MIPS32R5.


================
Comment at: lib/Target/Mips/MipsInstrInfo.td:2587-2592
+  def : MipsInstAlias<"mfgc0 $rt, $rd",
+                      (MFGC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>,
+                      ISA_MIPS32, ASE_VIRT;
+  def : MipsInstAlias<"mtgc0 $rt, $rd",
+                      (MTGC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>,
+                      ISA_MIPS32, ASE_VIRT;
----------------
These aliases should be guarded for MIPS32R5.


Repository:
  rL LLVM

https://reviews.llvm.org/D44905