[llvm] r329130 - [AArch64] Adjust the cost model for Exynos M3

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Tue Apr  3 15:57:17 2018
New Revision: 329130

URL: http://llvm.org/viewvc/llvm-project?rev=329130&view=rev
Log:
[AArch64] Adjust the cost model for Exynos M3

Fix typo and simplify matching expression.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td?rev=329130&r1=329129&r2=329130&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td Tue Apr  3 15:57:17 2018
@@ -109,15 +109,15 @@ def M3UnitNSHF : ProcResGroup<[M3UnitNSH
 //===----------------------------------------------------------------------===//
 // Predicates.
 
-def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
-                                            MI->getOperand(0).isReg() &&
-                                            MI->getOperand(0).getReg() != AArch64::LR}]>;
-def M3ResetFastPred      : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
-def M3RotateFastPred     : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
-                                             MI->getOpcode() == AArch64::EXTRXrri) &&
-                                            MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
-                                            MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
-def M3ShiftLeftFastPred  : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
+def M3BranchLinkFastPred  : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
+                                             MI->getOperand(0).isReg() &&
+                                             MI->getOperand(0).getReg() != AArch64::LR}]>;
+def M3ResetFastPred       : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
+def M3RotateRightFastPred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
+                                              MI->getOpcode() == AArch64::EXTRXrri) &&
+                                             MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
+                                             MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
+def M3ShiftLeftFastPred   : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
 
 //===----------------------------------------------------------------------===//
 // Coarse scheduling model.
@@ -143,8 +143,8 @@ def M3WriteC2 : SchedWriteRes<[M3UnitC]>
 def M3WriteAX : SchedWriteVariant<[SchedVar<M3ResetFastPred,     [M3WriteZ0]>,
                                    SchedVar<M3ShiftLeftFastPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,         [M3WriteAA]>]>;
-def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotateFastPred,    [M3WriteA1]>,
-                                   SchedVar<NoSchedPred,         [M3WriteAA]>]>;
+def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotateRightFastPred, [M3WriteA1]>,
+                                   SchedVar<NoSchedPred,           [M3WriteAA]>]>;
 
 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
 def M3WriteBX : SchedWriteVariant<[SchedVar<M3BranchLinkFastPred, [M3WriteAB]>,
@@ -509,7 +509,7 @@ def : InstRW<[M3WriteZ0], (instregex "^M
 // Divide and multiply instructions.
 
 // Miscellaneous instructions.
-def : InstRW<[M3WriteAY], (instregex "^EXTR[WX]rri")>;
+def : InstRW<[M3WriteAY], (instrs EXTRWrri, EXTRXrri)>;
 
 // Load instructions.
 def : InstRW<[M3WriteLD,