[PATCH] D45229: [MI-sched] schedule following instruction latencies

[Sirish Pande via Phabricator via llvm-commits]

SirishP added a comment.

I think we should ask backend if we want to gang up loads and stores, and if we do want to gang up loads and stores, then how many should we be ganging up together. Ganging up lots of loads may result in high register pressure.


https://reviews.llvm.org/D45229