[PATCH] D45183: [CodeGen]Add NoVRegs property on PostRASink and ShrinkWrap

[Jun Bum Lim via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL329095: [CodeGen]Add NoVRegs property on PostRASink and ShrinkWrap (authored by junbuml, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D45183?vs=140807&id=140831#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D45183

Files:
  llvm/trunk/lib/CodeGen/MachineSink.cpp
  llvm/trunk/lib/CodeGen/ShrinkWrap.cpp
  llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp
  llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp


Index: llvm/trunk/lib/CodeGen/MachineSink.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp
@@ -953,6 +953,11 @@
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+      MachineFunctionProperties::Property::NoVRegs);
+  }
+
 private:
   /// Track which registers have been modified and used.
   BitVector ModifiedRegs, UsedRegs;
Index: llvm/trunk/lib/CodeGen/ShrinkWrap.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/ShrinkWrap.cpp
+++ llvm/trunk/lib/CodeGen/ShrinkWrap.cpp
@@ -219,6 +219,11 @@
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+      MachineFunctionProperties::Property::NoVRegs);
+  }
+
   StringRef getPassName() const override { return "Shrink Wrapping analysis"; }
 
   /// \brief Perform the shrink-wrapping analysis and update
Index: llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp
===================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -238,9 +238,11 @@
   disablePass(&TailDuplicateID);
   disablePass(&StackMapLivenessID);
   disablePass(&LiveDebugValuesID);
+  disablePass(&PostRAMachineSinkingID);
   disablePass(&PostRASchedulerID);
   disablePass(&FuncletLayoutID);
   disablePass(&PatchableFunctionID);
+  disablePass(&ShrinkWrapID);
 
   // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
   // it here does nothing.  But since we need it for correctness when lowering
Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
===================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -264,16 +264,15 @@
   // virtual registers. Consider removing their restrictions and re-enabling
   // them.
 
-  // Has no asserts of its own, but was not written to handle virtual regs.
-  disablePass(&ShrinkWrapID);
-
   // These functions all require the NoVRegs property.
   disablePass(&MachineCopyPropagationID);
+  disablePass(&PostRAMachineSinkingID);
   disablePass(&PostRASchedulerID);
   disablePass(&FuncletLayoutID);
   disablePass(&StackMapLivenessID);
   disablePass(&LiveDebugValuesID);
   disablePass(&PatchableFunctionID);
+  disablePass(&ShrinkWrapID);
 
   TargetPassConfig::addPostRegAlloc();
 }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D45183.140831.patch
Type: text/x-patch
Size: 2751 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180403/f16fbe1a/attachment.bin>