[llvm] r328988 - [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 2 10:09:20 PDT 2018
Author: dpreobra
Date: Mon Apr 2 10:09:20 2018
New Revision: 328988
URL: http://llvm.org/viewvc/llvm-project?rev=328988&view=rev
Log:
[AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16
See bug 36847: https://bugs.llvm.org/show_bug.cgi?id=36847
Differential Revision: https://reviews.llvm.org/D45097
Reviewers: artem.tamazov, arsenm, timcorringham
Modified:
llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
llvm/trunk/test/MC/AMDGPU/vop1-gfx9.s
llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s
llvm/trunk/test/MC/AMDGPU/vop_dpp.s
llvm/trunk/test/MC/AMDGPU/vop_sdwa.s
llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_gfx9.txt
llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
Modified: llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td?rev=328988&r1=328987&r2=328988&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td Mon Apr 2 10:09:20 2018
@@ -382,6 +382,10 @@ let SubtargetPredicate = isGFX9 in {
def V_SWAP_B32 : VOP1_Pseudo <"v_swap_b32", VOP_SWAP_I32, [], 1>;
}
+defm V_SAT_PK_U8_I16 : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
+defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>;
+defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;
+
} // End SubtargetPredicate = isGFX9
//===----------------------------------------------------------------------===//
@@ -612,6 +616,10 @@ defm V_SIN_F16 : VOP1_Real_vi
defm V_COS_F16 : VOP1_Real_vi <0x4a>;
defm V_SWAP_B32 : VOP1Only_Real_vi <0x51>;
+defm V_SAT_PK_U8_I16 : VOP1_Real_vi<0x4f>;
+defm V_CVT_NORM_I16_F16 : VOP1_Real_vi<0x4d>;
+defm V_CVT_NORM_U16_F16 : VOP1_Real_vi<0x4e>;
+
// Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
// indexing mode. vdst can't be treated as a def for codegen purposes,
// and an implicit use and def of the super register should be added.
Modified: llvm/trunk/test/MC/AMDGPU/vop1-gfx9.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop1-gfx9.s?rev=328988&r1=328987&r2=328988&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop1-gfx9.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop1-gfx9.s Mon Apr 2 10:09:20 2018
@@ -11,3 +11,31 @@ v_swap_b32 v1, v2
v_swap_b32_e32 v1, v2
// GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e]
// NOVI: :1: error: instruction not supported on this GPU
+
+v_cvt_norm_i16_f16 v5, v1
+// GFX9: v_cvt_norm_i16_f16_e32 v5, v1 ; encoding: [0x01,0x9b,0x0a,0x7e]
+// NOVI: error: instruction not supported on this GPU
+
+v_cvt_norm_i16_f16 v5, -4.0
+// GFX9: v_cvt_norm_i16_f16_e32 v5, -4.0 ; encoding: [0xf7,0x9a,0x0a,0x7e]
+// NOVI: error: instruction not supported on this GPU
+
+v_cvt_norm_i16_f16 v5, 0xfe0b
+// GFX9: v_cvt_norm_i16_f16_e32 v5, 0xfe0b ; encoding: [0xff,0x9a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+// NOVI: error: instruction not supported on this GPU
+
+v_cvt_norm_u16_f16 v5, s101
+// GFX9: v_cvt_norm_u16_f16_e32 v5, s101 ; encoding: [0x65,0x9c,0x0a,0x7e]
+// NOVI: error: instruction not supported on this GPU
+
+v_sat_pk_u8_i16 v255, v1
+// GFX9: v_sat_pk_u8_i16_e32 v255, v1 ; encoding: [0x01,0x9f,0xfe,0x7f]
+// NOVI: error: instruction not supported on this GPU
+
+v_sat_pk_u8_i16 v5, -1
+// GFX9: v_sat_pk_u8_i16_e32 v5, -1 ; encoding: [0xc1,0x9e,0x0a,0x7e]
+// NOVI: error: instruction not supported on this GPU
+
+v_sat_pk_u8_i16 v5, 0x3f717273
+// GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+// NOVI: error: instruction not supported on this GPU
Modified: llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s?rev=328988&r1=328987&r2=328988&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s Mon Apr 2 10:09:20 2018
@@ -421,3 +421,27 @@ v_interp_p2_legacy_f16 v5, v2, attr0.x,
v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_cvt_norm_i16_f16_e64 v5, -v1
+// GFX9: v_cvt_norm_i16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20]
+// NOVI: error: instruction not supported on this GPU
+
+v_cvt_norm_i16_f16_e64 v5, |v1|
+// GFX9: v_cvt_norm_i16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00]
+// NOVI: error: instruction not supported on this GPU
+
+v_cvt_norm_u16_f16_e64 v5, -v1
+// GFX9: v_cvt_norm_u16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x20]
+// NOVI: error: instruction not supported on this GPU
+
+v_cvt_norm_u16_f16_e64 v5, |v1|
+// GFX9: v_cvt_norm_u16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8e,0xd1,0x01,0x01,0x00,0x00]
+// NOVI: error: instruction not supported on this GPU
+
+v_sat_pk_u8_i16_e64 v5, -1
+// GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00]
+// NOVI: error: instruction not supported on this GPU
+
+v_sat_pk_u8_i16_e64 v5, v255
+// GFX9: v_sat_pk_u8_i16_e64 v5, v255 ; encoding: [0x05,0x00,0x8f,0xd1,0xff,0x01,0x00,0x00]
+// NOVI: error: instruction not supported on this GPU
Modified: llvm/trunk/test/MC/AMDGPU/vop_dpp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop_dpp.s?rev=328988&r1=328987&r2=328988&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop_dpp.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop_dpp.s Mon Apr 2 10:09:20 2018
@@ -335,6 +335,21 @@ v_sin_f16 v1, v0 row_shl:1 row_mask:0xa
// VI9: v_cos_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x94,0x02,0x7e,0x00,0x01,0x09,0xa1]
v_cos_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
+// GFX9: v_cvt_norm_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+// NOSICI: error
+// NOVI: error
+v_cvt_norm_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+
+// GFX9: v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+// NOSICI: error
+// NOVI: error
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+
+// GFX9: v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+// NOSICI: error
+// NOVI: error
+v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+
//===----------------------------------------------------------------------===//
// Check VOP2 opcodes
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/AMDGPU/vop_sdwa.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop_sdwa.s?rev=328988&r1=328987&r2=328988&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop_sdwa.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop_sdwa.s Mon Apr 2 10:09:20 2018
@@ -340,6 +340,31 @@ v_sin_f16 v1, v0 dst_sel:DWORD dst_unuse
// GFX89: v_cos_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x94,0x02,0x7e,0x00,0x06,0x05,0x00]
v_cos_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX9: v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+// NOSICI: error
+// NOVI: error
+v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+
+// GFX9: v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+// NOSICI: error
+// NOVI: error
+v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+
+// GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+// NOSICI: error
+// NOVI: error
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+
+// GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+// NOSICI: error
+// NOVI: error
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+
+// GFX9: v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+// NOSICI: error
+// NOVI: error
+v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+
//===----------------------------------------------------------------------===//
// Check VOP2 opcodes
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt?rev=328988&r1=328987&r2=328988&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt Mon Apr 2 10:09:20 2018
@@ -224,6 +224,24 @@
# GFX9: v_cos_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x94,0x02,0x7e,0x00,0x06,0x05,0x00]
0xf9 0x94 0x02 0x7e 0x00 0x06 0x05 0x00
+# GFX9: v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x05,0x00
+
+# GFX9: v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00
+
+# GFX9: v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00
+
+# GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00
+
+# GFX9: v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00
+
+# GFX9: v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00
+
#-----------------------------------------------------------------------------#
# VOP2
#-----------------------------------------------------------------------------#
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_gfx9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_gfx9.txt?rev=328988&r1=328987&r2=328988&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_gfx9.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_gfx9.txt Mon Apr 2 10:09:20 2018
@@ -2,3 +2,24 @@
# GFX9: v_swap_b32 v1, v2 ; encoding: [0x02,0xa3,0x02,0x7e]
0x02 0xa3 0x02 0x7e
+
+# GFX9: v_cvt_norm_i16_f16_e32 v255, v1 ; encoding: [0x01,0x9b,0xfe,0x7f]
+0x01,0x9b,0xfe,0x7f
+
+# GFX9: v_cvt_norm_i16_f16_e32 v5, 0.5 ; encoding: [0xf0,0x9a,0x0a,0x7e]
+0xf0,0x9a,0x0a,0x7e
+
+# GFX9: v_cvt_norm_i16_f16_e32 v5, 0x3456 ; encoding: [0xff,0x9a,0x0a,0x7e,0x56,0x34,0x00,0x00]
+0xff,0x9a,0x0a,0x7e,0x56,0x34,0x00,0x00
+
+# GFX9: v_cvt_norm_u16_f16_e32 v5, s101 ; encoding: [0x65,0x9c,0x0a,0x7e]
+0x65,0x9c,0x0a,0x7e
+
+# GFX9: v_sat_pk_u8_i16_e32 v5, v255 ; encoding: [0xff,0x9f,0x0a,0x7e]
+0xff,0x9f,0x0a,0x7e
+
+# GFX9: v_sat_pk_u8_i16_e32 v5, -1 ; encoding: [0xc1,0x9e,0x0a,0x7e]
+0xc1,0x9e,0x0a,0x7e
+
+# GFX9: v_sat_pk_u8_i16_e32 v5, 0x3f717273 ; encoding: [0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+0xff,0x9e,0x0a,0x7e,0x73,0x72,0x71,0x3f
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt?rev=328988&r1=328987&r2=328988&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt Mon Apr 2 10:09:20 2018
@@ -671,3 +671,24 @@
# GFX9: v_add_f64 v[5:6], xnack_mask, v[2:3] ; encoding: [0x05,0x00,0x80,0xd2,0x68,0x04,0x02,0x00]
0x05,0x00,0x80,0xd2,0x68,0x04,0x02,0x00
+
+# GFX9: v_cvt_norm_i16_f16_e64 v5, -4.0 ; encoding: [0x05,0x00,0x8d,0xd1,0xf7,0x00,0x00,0x00]
+0x05,0x00,0x8d,0xd1,0xf7,0x00,0x00,0x00
+
+# GFX9: v_cvt_norm_i16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20]
+0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20
+
+# GFX9: v_cvt_norm_i16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00]
+0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00
+
+# GFX9: v_cvt_norm_u16_f16_e64 v255, v1 ; encoding: [0xff,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00]
+0xff,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00
+
+# GFX9: v_cvt_norm_u16_f16_e64 v5, v255 ; encoding: [0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00]
+0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00
+
+# GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00]
+0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00
+
+# GFX9: v_sat_pk_u8_i16_e64 v255, v1 ; encoding: [0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00]
+0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00
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