[llvm] r328981 - [Hexagon] Clean up some code in HexagonAsmPrinter, NFC
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 2 08:06:55 PDT 2018
Author: kparzysz
Date: Mon Apr 2 08:06:55 2018
New Revision: 328981
URL: http://llvm.org/viewvc/llvm-project?rev=328981&view=rev
Log:
[Hexagon] Clean up some code in HexagonAsmPrinter, NFC
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.h
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=328981&r1=328980&r2=328981&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Mon Apr 2 08:06:55 2018
@@ -62,10 +62,6 @@ void HexagonLowerToMC(const MCInstrInfo
#define DEBUG_TYPE "asm-printer"
-static cl::opt<bool> AlignCalls(
- "hexagon-align-calls", cl::Hidden, cl::init(true),
- cl::desc("Insert falign after call instruction for Hexagon target"));
-
// Given a scalar register return its pair.
inline static unsigned getHexagonRegisterPair(unsigned Reg,
const MCRegisterInfo *RI) {
@@ -76,16 +72,13 @@ inline static unsigned getHexagonRegiste
return Pair;
}
-HexagonAsmPrinter::HexagonAsmPrinter(TargetMachine &TM,
- std::unique_ptr<MCStreamer> Streamer)
- : AsmPrinter(TM, std::move(Streamer)) {}
-
void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
- default: llvm_unreachable ("<unknown operand type>");
+ default:
+ llvm_unreachable ("<unknown operand type>");
case MachineOperand::MO_Register:
O << HexagonInstPrinter::getRegisterName(MO.getReg());
return;
@@ -112,8 +105,8 @@ void HexagonAsmPrinter::printOperand(con
// for the case in which the basic block is reachable by a fall through but
// through an indirect from a jump table. In this case, the jump table
// will contain a label not defined by AsmPrinter.
-bool HexagonAsmPrinter::
-isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
+bool HexagonAsmPrinter::isBlockOnlyReachableByFallthrough(
+ const MachineBasicBlock *MBB) const {
if (MBB->hasAddressTaken())
return false;
return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
@@ -167,7 +160,8 @@ bool HexagonAsmPrinter::PrintAsmOperand(
}
bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
- unsigned OpNo, unsigned AsmVariant,
+ unsigned OpNo,
+ unsigned AsmVariant,
const char *ExtraCode,
raw_ostream &O) {
if (ExtraCode && ExtraCode[0])
@@ -183,10 +177,10 @@ bool HexagonAsmPrinter::PrintAsmMemoryOp
if (Offset.isImm()) {
if (Offset.getImm())
- O << " + #" << Offset.getImm();
- }
- else
+ O << "+#" << Offset.getImm();
+ } else {
llvm_unreachable("Unimplemented");
+ }
return false;
}
@@ -285,7 +279,8 @@ void HexagonAsmPrinter::HexagonProcessIn
unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
switch (Inst.getOpcode()) {
- default: return;
+ default:
+ return;
case Hexagon::A2_iconst: {
Inst.setOpcode(Hexagon::A2_addi);
@@ -300,30 +295,40 @@ void HexagonAsmPrinter::HexagonProcessIn
break;
}
- case Hexagon::A2_tfrf:
+ case Hexagon::A2_tfrf: {
+ const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext);
Inst.setOpcode(Hexagon::A2_paddif);
- Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
+ Inst.addOperand(MCOperand::createExpr(Zero));
break;
+ }
- case Hexagon::A2_tfrt:
+ case Hexagon::A2_tfrt: {
+ const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext);
Inst.setOpcode(Hexagon::A2_paddit);
- Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
+ Inst.addOperand(MCOperand::createExpr(Zero));
break;
+ }
- case Hexagon::A2_tfrfnew:
+ case Hexagon::A2_tfrfnew: {
+ const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext);
Inst.setOpcode(Hexagon::A2_paddifnew);
- Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
+ Inst.addOperand(MCOperand::createExpr(Zero));
break;
+ }
- case Hexagon::A2_tfrtnew:
+ case Hexagon::A2_tfrtnew: {
+ const MCConstantExpr *Zero = MCConstantExpr::create(0, OutContext);
Inst.setOpcode(Hexagon::A2_padditnew);
- Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
+ Inst.addOperand(MCOperand::createExpr(Zero));
break;
+ }
- case Hexagon::A2_zxtb:
+ case Hexagon::A2_zxtb: {
+ const MCConstantExpr *C255 = MCConstantExpr::create(255, OutContext);
Inst.setOpcode(Hexagon::A2_andir);
- Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, OutContext)));
+ Inst.addOperand(MCOperand::createExpr(C255));
break;
+ }
// "$dst = CONST64(#$src1)",
case Hexagon::CONST64:
@@ -525,10 +530,12 @@ void HexagonAsmPrinter::HexagonProcessIn
bool Success = MO.getExpr()->evaluateAsAbsolute(Imm);
if (Success && Imm < 0) {
const MCExpr *MOne = MCConstantExpr::create(-1, OutContext);
- TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(MOne, OutContext)));
+ const HexagonMCExpr *E = HexagonMCExpr::create(MOne, OutContext);
+ TmpInst.addOperand(MCOperand::createExpr(E));
} else {
const MCExpr *Zero = MCConstantExpr::create(0, OutContext);
- TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(Zero, OutContext)));
+ const HexagonMCExpr *E = HexagonMCExpr::create(Zero, OutContext);
+ TmpInst.addOperand(MCOperand::createExpr(E));
}
TmpInst.addOperand(MO);
MappedInst = TmpInst;
@@ -569,9 +576,9 @@ void HexagonAsmPrinter::HexagonProcessIn
MO.setReg(High);
// Add a new operand for the second register in the pair.
MappedInst.addOperand(MCOperand::createReg(Low));
- MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
- ? Hexagon::C2_ccombinewnewt
- : Hexagon::C2_ccombinewnewf);
+ MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew
+ ? Hexagon::C2_ccombinewnewt
+ : Hexagon::C2_ccombinewnewf);
return;
}
@@ -615,6 +622,7 @@ void HexagonAsmPrinter::HexagonProcessIn
MappedInst = TmpInst;
return;
}
+
case Hexagon::V6_vdd0: {
MCInst TmpInst;
assert (Inst.getOperand(0).isReg() &&
@@ -627,6 +635,7 @@ void HexagonAsmPrinter::HexagonProcessIn
MappedInst = TmpInst;
return;
}
+
case Hexagon::V6_vL32Ub_pi:
case Hexagon::V6_vL32b_cur_pi:
case Hexagon::V6_vL32b_nt_cur_pi:
@@ -735,12 +744,10 @@ void HexagonAsmPrinter::HexagonProcessIn
case Hexagon::V6_vS32b_srls_pi:
MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
return;
-
}
}
-/// printMachineInstruction -- Print out a single Hexagon MI in Darwin syntax to
-/// the current output stream.
+/// Print out a single Hexagon MI to the current output stream.
void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst MCB;
MCB.setOpcode(Hexagon::BUNDLE);
@@ -764,11 +771,11 @@ void HexagonAsmPrinter::EmitInstruction(
if (MI->isBundle() && HII.getBundleNoShuf(*MI))
HexagonMCInstrInfo::setMemReorderDisabled(MCB);
- bool Ok = HexagonMCInstrInfo::canonicalizePacket(
- MCII, *Subtarget, OutStreamer->getContext(), MCB, nullptr);
- assert(Ok);
- (void)Ok;
- if(HexagonMCInstrInfo::bundleSize(MCB) == 0)
+ MCContext &Ctx = OutStreamer->getContext();
+ bool Ok = HexagonMCInstrInfo::canonicalizePacket(MCII, *Subtarget, Ctx,
+ MCB, nullptr);
+ assert(Ok); (void)Ok;
+ if (HexagonMCInstrInfo::bundleSize(MCB) == 0)
return;
OutStreamer->EmitInstruction(MCB, getSubtargetInfo());
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.h?rev=328981&r1=328980&r2=328981&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.h Mon Apr 2 08:06:55 2018
@@ -18,7 +18,8 @@
#include "HexagonSubtarget.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include <memory>
+#include "llvm/MC/MCStreamer.h"
+#include <utility>
namespace llvm {
@@ -32,7 +33,8 @@ class TargetMachine;
public:
explicit HexagonAsmPrinter(TargetMachine &TM,
- std::unique_ptr<MCStreamer> Streamer);
+ std::unique_ptr<MCStreamer> Streamer)
+ : AsmPrinter(TM, std::move(Streamer)) {}
bool runOnMachineFunction(MachineFunction &Fn) override {
Subtarget = &Fn.getSubtarget<HexagonSubtarget>();
@@ -43,13 +45,11 @@ class TargetMachine;
return "Hexagon Assembly Printer";
}
- bool isBlockOnlyReachableByFallthrough(
- const MachineBasicBlock *MBB) const override;
+ bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
+ const override;
void EmitInstruction(const MachineInstr *MI) override;
-
- void HexagonProcessInstruction(MCInst &Inst,
- const MachineInstr &MBB);
+ void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB);
void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
@@ -58,8 +58,6 @@ class TargetMachine;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &OS) override;
-
- static const char *getRegisterName(unsigned RegNo);
};
} // end namespace llvm
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