[llvm] r328946 - [X86] Give ADC8/16/32/64mi the same scheduling information as ADC8/16/32/64mr and SBB8/16/32/64mi.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 1 14:54:24 PDT 2018
Author: ctopper
Date: Sun Apr 1 14:54:24 2018
New Revision: 328946
URL: http://llvm.org/viewvc/llvm-project?rev=328946&view=rev
Log:
[X86] Give ADC8/16/32/64mi the same scheduling information as ADC8/16/32/64mr and SBB8/16/32/64mi.
It doesn't make a lot of sense that it would be different.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=328946&r1=328945&r2=328946&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sun Apr 1 14:54:24 2018
@@ -2014,15 +2014,15 @@ def BWWriteResGroup99 : SchedWriteRes<[B
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
-def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi",
- "XCHG(8|16|32|64)rm")>;
+def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
-def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr",
+def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mi",
+ "ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"ROL(8|16|32|64)mCL",
"SAR(8|16|32|64)mCL",
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=328946&r1=328945&r2=328946&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sun Apr 1 14:54:24 2018
@@ -2110,15 +2110,15 @@ def HWWriteResGroup68 : SchedWriteRes<[H
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
-def: InstRW<[HWWriteResGroup68], (instregex "ADC(8|16|32|64)mi",
- "XCHG(8|16|32|64)rm")>;
+def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
-def: InstRW<[HWWriteResGroup69], (instregex "ADC(8|16|32|64)mr",
+def: InstRW<[HWWriteResGroup69], (instregex "ADC(8|16|32|64)mi",
+ "ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"ROL(8|16|32|64)mCL",
"SAR(8|16|32|64)mCL",
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=328946&r1=328945&r2=328946&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sun Apr 1 14:54:24 2018
@@ -2076,19 +2076,13 @@ def: InstRW<[SKLWriteResGroup117], (inst
"SHL(8|16|32|64)mCL",
"SHR(8|16|32|64)mCL")>;
-def SKLWriteResGroup118 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
- let Latency = 8;
- let NumMicroOps = 6;
- let ResourceCycles = [1,1,1,3];
-}
-def: InstRW<[SKLWriteResGroup118], (instregex "ADC(8|16|32|64)mi")>;
-
def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
-def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mr",
+def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mi",
+ "ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"SBB(8|16|32|64)mi",
"SBB(8|16|32|64)mr")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=328946&r1=328945&r2=328946&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Apr 1 14:54:24 2018
@@ -4416,19 +4416,13 @@ def: InstRW<[SKXWriteResGroup128], (inst
"SHL(8|16|32|64)mCL",
"SHR(8|16|32|64)mCL")>;
-def SKXWriteResGroup129 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
- let Latency = 8;
- let NumMicroOps = 6;
- let ResourceCycles = [1,1,1,3];
-}
-def: InstRW<[SKXWriteResGroup129], (instregex "ADC(8|16|32|64)mi")>;
-
def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
-def: InstRW<[SKXWriteResGroup130], (instregex "ADC(8|16|32|64)mr",
+def: InstRW<[SKXWriteResGroup130], (instregex "ADC(8|16|32|64)mi",
+ "ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"SBB(8|16|32|64)mi",
"SBB(8|16|32|64)mr")>;
More information about the llvm-commits
mailing list