[llvm] r328907 - Fix a bunch of typoes. NFC
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 30 15:22:31 PDT 2018
Author: maskray
Date: Fri Mar 30 15:22:31 2018
New Revision: 328907
URL: http://llvm.org/viewvc/llvm-project?rev=328907&view=rev
Log:
Fix a bunch of typoes. NFC
Modified:
llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/CodeGen/StackColoring.cpp
llvm/trunk/lib/Target/BPF/BPFISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/trunk/lib/Transforms/Scalar/ADCE.cpp
llvm/trunk/lib/Transforms/Scalar/LICM.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp
Modified: llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp Fri Mar 30 15:22:31 2018
@@ -245,7 +245,7 @@ static void initialize(TargetLibraryInfo
TLI.setUnavailable(LibFunc_tanhf);
}
- // Win32 does *not* provide provide these functions, but they are
+ // Win32 does *not* provide these functions, but they are
// generally available on POSIX-compliant systems:
TLI.setUnavailable(LibFunc_access);
TLI.setUnavailable(LibFunc_bcmp);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Mar 30 15:22:31 2018
@@ -9677,7 +9677,7 @@ void SelectionDAGBuilder::lowerWorkItem(
});
// Rearrange the case blocks so that the last one falls through if possible
- // without without changing the order of probabilities.
+ // without changing the order of probabilities.
for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
--I;
if (I->Prob > W.LastCluster->Prob)
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Mar 30 15:22:31 2018
@@ -2300,7 +2300,7 @@ bool SelectionDAGISel::IsLegalToFold(SDV
// If Root use can somehow reach N through a path that that doesn't contain
// U then folding N would create a cycle. e.g. In the following
- // diagram, Root can reach N through X. If N is folded into into Root, then
+ // diagram, Root can reach N through X. If N is folded into Root, then
// X is both a predecessor and a successor of U.
//
// [N*] //
Modified: llvm/trunk/lib/CodeGen/StackColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackColoring.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackColoring.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackColoring.cpp Fri Mar 30 15:22:31 2018
@@ -993,7 +993,7 @@ void StackColoring::remapInstructions(De
// the calculated range then it means that the alloca usage moved
// outside of the lifetime markers, or that the user has a bug.
// NOTE: Alloca address calculations which happen outside the lifetime
- // zone are are okay, despite the fact that we don't have a good way
+ // zone are okay, despite the fact that we don't have a good way
// for validating all of the usages of the calculation.
#ifndef NDEBUG
bool TouchesMemory = I.mayLoad() || I.mayStore();
Modified: llvm/trunk/lib/Target/BPF/BPFISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFISelDAGToDAG.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/BPF/BPFISelDAGToDAG.cpp Fri Mar 30 15:22:31 2018
@@ -609,7 +609,7 @@ void BPFDAGToDAGISel::PreprocessTrunc(SD
// %2 = PHI %0, <%bb.1>, %1, <%bb.3>
// Trace each incoming definition, e.g., (%0, %bb.1) and (%1, %bb.3)
// The AND operation can be removed if both %0 in %bb.1 and %1 in
- // %bb.3 are defined with with a load matching the MaskN.
+ // %bb.3 are defined with a load matching the MaskN.
DEBUG(dbgs() << "Check PHI Insn: "; MII->dump(); dbgs() << '\n');
unsigned PrevReg = -1;
for (unsigned i = 0; i < MII->getNumOperands(); ++i) {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp Fri Mar 30 15:22:31 2018
@@ -259,7 +259,7 @@ bool Coloring::color() {
Colors[C] = ColorC;
}
- // Explicitly assign "None" all all uncolored nodes.
+ // Explicitly assign "None" to all uncolored nodes.
for (unsigned I = 0; I != Order.size(); ++I)
if (Colors.count(I) == 0)
Colors[I] = ColorKind::None;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Fri Mar 30 15:22:31 2018
@@ -414,7 +414,7 @@ HexagonTargetLowering::LowerCall(TargetL
VA.getLocVT().getStoreSizeInBits() >> 3);
if (Flags.isByVal()) {
// The argument is a struct passed by value. According to LLVM, "Arg"
- // is is pointer.
+ // is a pointer.
MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
Flags, DAG, dl));
} else {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp Fri Mar 30 15:22:31 2018
@@ -16,7 +16,7 @@
// The basic approach looks for sequence of predicated jump, compare instruciton
// that genereates the predicate and, the feeder to the predicate. Once it finds
-// all, it collapses compare and jump instruction into a new valu jump
+// all, it collapses compare and jump instruction into a new value jump
// intstructions.
//
//===----------------------------------------------------------------------===//
@@ -159,7 +159,7 @@ static bool canBeFeederToNewValueJump(co
}
assert(HadDef);
- // Make sure there there is no 'def' or 'use' of any of the uses of
+ // Make sure there is no 'def' or 'use' of any of the uses of
// feeder insn between it's definition, this MI and jump, jmpInst
// skipping compare, cmpInst.
// Here's the example.
@@ -287,8 +287,8 @@ static bool canCompareBeNewValueJump(con
if (cmpReg1 == cmpOp2)
return false;
- // Make sure that that second register is not from COPY
- // At machine code level, we don't need this, but if we decide
+ // Make sure that the second register is not from COPY
+ // at machine code level, we don't need this, but if we decide
// to move new value jump prior to RA, we would be needing this.
MachineRegisterInfo &MRI = MF.getRegInfo();
if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Fri Mar 30 15:22:31 2018
@@ -598,7 +598,7 @@ bool MipsInstrInfo::verifyInstruction(co
case Mips::DINS:
return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
case Mips::DINSM:
- // The ISA spec has a subtle difference difference between dinsm and dextm
+ // The ISA spec has a subtle difference between dinsm and dextm
// in that it says:
// 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
// To make the bounds checks similar, the range 1 < size <= 64 is checked
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Fri Mar 30 15:22:31 2018
@@ -663,8 +663,7 @@ protected:
// instruction.
CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
- // Encode any extra stack stack adjustments (done via push
- // instructions).
+ // Encode any extra stack adjustments (done via push instructions).
CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
}
Modified: llvm/trunk/lib/Transforms/Scalar/ADCE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ADCE.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ADCE.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ADCE.cpp Fri Mar 30 15:22:31 2018
@@ -174,8 +174,8 @@ class AggressiveDeadCodeElimination {
/// marked live.
void markLiveBranchesFromControlDependences();
- /// Remove instructions not marked live, return if any any instruction
- /// was removed.
+ /// Remove instructions not marked live, return if any instruction was
+ /// removed.
bool removeDeadInstructions();
/// Identify connected sections of the control flow graph which have
Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Fri Mar 30 15:22:31 2018
@@ -1335,7 +1335,7 @@ bool llvm::promoteLoopAccessesToScalars(
// If a store dominates all exit blocks, it is safe to sink.
// As explained above, if an exit block was executed, a dominating
- // store must have been been executed at least once, so we are not
+ // store must have been executed at least once, so we are not
// introducing stores on paths that did not have them.
// Note that this only looks at explicit exit blocks. If we ever
// start sinking stores into unwind edges (see above), this will break.
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Fri Mar 30 15:22:31 2018
@@ -2660,7 +2660,7 @@ TreePatternNode *TreePattern::ParseTreeP
// node (which is hard-coded to have either zero or one result).
unsigned NumResults = GetNumNodeResults(Operator, CDP);
- // If the operator is an intrinsic, then this is just syntactic sugar for for
+ // If the operator is an intrinsic, then this is just syntactic sugar for
// (intrinsic_* <number>, ..children..). Pick the right intrinsic node, and
// convert the intrinsic name to a number.
if (Operator->isSubClassOf("Intrinsic")) {
Modified: llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp?rev=328907&r1=328906&r2=328907&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp Fri Mar 30 15:22:31 2018
@@ -551,7 +551,7 @@ void X86FoldTablesEmitter::updateTables(
}
} else if (MemInSize == RegInSize + 1 && MemOutSize + 1 == RegOutSize) {
// Store-Folding cases.
- // If the memory form instruction performs performs a store, the *output*
+ // If the memory form instruction performs a store, the *output*
// register of the register form instructions disappear and instead a
// memory *input* operand appears in the memory form instruction.
// For example:
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