[llvm] r328867 - [X86][BtVer2] Add missing ReadAfterLd to RM variants of AVX horizontal adds and
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 30 07:48:09 PDT 2018
Author: adibiagio
Date: Fri Mar 30 07:48:08 2018
New Revision: 328867
URL: http://llvm.org/viewvc/llvm-project?rev=328867&view=rev
Log:
[X86][BtVer2] Add missing ReadAfterLd to RM variants of AVX horizontal adds and
most vector logic instructions.
Fixed a few InstRW that forgot to specify a ReadAfterLd for the register input
operand.
Modified:
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-1.s
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-2.s
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=328867&r1=328866&r2=328867&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Fri Mar 30 07:48:08 2018
@@ -395,7 +395,8 @@ def JWriteFHAddYLd: SchedWriteRes<[JLAGU
let Latency = 8;
let ResourceCycles = [2, 2, 2];
}
-def : InstRW<[JWriteFHAddYLd], (instrs VHADDPDYrm, VHADDPSYrm, VHSUBPDYrm, VHSUBPSYrm)>;
+def : InstRW<[JWriteFHAddYLd, ReadAfterLd], (instrs VHADDPDYrm, VHADDPSYrm,
+ VHSUBPDYrm, VHSUBPSYrm)>;
////////////////////////////////////////////////////////////////////////////////
// Carry-less multiplication instructions.
@@ -510,10 +511,14 @@ def : InstRW<[JWriteFLogic], (instrs ORP
def JWriteFLogicLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
let Latency = 6;
}
-def : InstRW<[JWriteFLogicLd], (instrs ORPDrm, ORPSrm, VORPDrm, VORPSrm,
- XORPDrm, XORPSrm, VXORPDrm, VXORPSrm,
- ANDPDrm, ANDPSrm, VANDPDrm, VANDPSrm,
- ANDNPDrm, ANDNPSrm, VANDNPDrm, VANDNPSrm)>;
+def : InstRW<[JWriteFLogicLd, ReadAfterLd], (instrs ORPDrm, ORPSrm,
+ VORPDrm, VORPSrm,
+ XORPDrm, XORPSrm,
+ VXORPDrm, VXORPSrm,
+ ANDPDrm, ANDPSrm,
+ VANDPDrm, VANDPSrm,
+ ANDNPDrm, ANDNPSrm,
+ VANDNPDrm, VANDNPSrm)>;
def JWriteFLogicY: SchedWriteRes<[JFPU01, JFPX]> {
let ResourceCycles = [2, 2];
@@ -529,10 +534,10 @@ def JWriteFLogicYLd: SchedWriteRes<[JLAG
let ResourceCycles = [2, 2, 2];
let NumMicroOps = 2;
}
-def : InstRW<[JWriteFLogicYLd], (instrs VORPDYrm, VORPSYrm,
- VXORPDYrm, VXORPSYrm,
- VANDPDYrm, VANDPSYrm,
- VANDNPDYrm, VANDNPSYrm)>;
+def : InstRW<[JWriteFLogicYLd, ReadAfterLd], (instrs VORPDYrm, VORPSYrm,
+ VXORPDYrm, VXORPSYrm,
+ VANDPDYrm, VANDPSYrm,
+ VANDNPDYrm, VANDNPSYrm)>;
def JWriteVDPPSY: SchedWriteRes<[JFPU1, JFPM, JFPA]> {
let Latency = 12;
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s?rev=328867&r1=328866&r2=328867&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s Fri Mar 30 07:48:08 2018
@@ -17,7 +17,7 @@ vhaddps (%rdi), %ymm1, %ymm2
# CHECK: Timeline view:
-# CHECK-NEXT: 01
-# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeER . .. vshufps $0, %xmm0, %xmm1, %xmm1
-# CHECK-NEXT: [0,1] D=eeeeeeeeER vhaddps (%rdi), %ymm1, %ymm2
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
+# CHECK: [0,0] DeER . . vshufps $0, %xmm0, %xmm1, %xmm1
+# CHECK-NEXT: [0,1] DeeeeeeeeER vhaddps (%rdi), %ymm1, %ymm2
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-1.s?rev=328867&r1=328866&r2=328867&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-1.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-1.s Fri Mar 30 07:48:08 2018
@@ -17,7 +17,6 @@ vandps (%rdi), %xmm1, %xmm2
# CHECK: Timeline view:
-# CHECK-NEXT: 01
-# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeER .. vaddps %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [0,1] D===eeeeeeER vandps (%rdi), %xmm1, %xmm2
+# CHECK: Index 012345678
+# CHECK: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [0,1] DeeeeeeER vandps (%rdi), %xmm1, %xmm2
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-2.s?rev=328867&r1=328866&r2=328867&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-2.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-2.s Fri Mar 30 07:48:08 2018
@@ -17,7 +17,6 @@ vandps (%rdi), %ymm1, %ymm2
# CHECK: Timeline view:
-# CHECK-NEXT: 01
-# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeER .. vaddps %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [0,1] .D==eeeeeeER vandps (%rdi), %ymm1, %ymm2
+# CHECK: Index 0123456789
+# CHECK: [0,0] DeeeER . vaddps %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [0,1] .DeeeeeeER vandps (%rdi), %ymm1, %ymm2
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