[PATCH] D45020: [mips] Accept 32-bit offsets for lb and lbu commands

[Simon Atanasyan via Phabricator via llvm-commits]

atanasyan created this revision.
atanasyan added a reviewer: sdardis.
Herald added a subscriber: arichardson.

`lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts larger offsets for these commands. If an offset does not fit in 16-bit range, `lb` command is translated into lui/lb or lui/addu/lb series. It's interesting that initially LLVM assembler supported this feature, but later it was broken.

The patch attempts to restore the support. However, some issues remain:

- LD, LH, LHu, LW commands have not been checked. Maybe the regression affects them too. I'm going to check it later.
- GAS accepts any 32-bit values as an offset. Now LLVM accepts signed 16-bit values and this patch extends the range to signed 32-bit offsets. In other words, the following code accepted by GAS and triggers an error for LLVM: ``` lb      $4, 0x80000004
  1. gas lui     a0, 0x8000 lb      a0, 4(a0) ``` It's unclear to me should we follow GAS in that case.
- In case of 64-bit pointers GAS accepts a 64-bit offset and translates it to the li/dsll/lb series of commands. LLVM still rejects it. Probably this feature has never been implemented in LVVM. This issue is for a separate patch. ``` lb      $4, 0x800000001
  1. gas li      a0, 0x8000 dsll    a0, a0,0x14 lb      a0, 4(a0) ```
- Definition of `mem_simm32` in this patch continues to use `simm16` for `MIOperandInfo` initialization. It's unclear to me should we change `simm16` to `simm32`. Thoughts?


Repository:
  rL LLVM

https://reviews.llvm.org/D45020

Files:
  lib/Target/Mips/AsmParser/MipsAsmParser.cpp
  lib/Target/Mips/MipsInstrInfo.td
  test/MC/Mips/micromips/invalid.s
  test/MC/Mips/micromips32r6/invalid.s
  test/MC/Mips/mips-expansions.s
  test/MC/Mips/mips32r5/invalid.s
  test/MC/Mips/mips32r6/invalid.s
  test/MC/Mips/mips64r5/invalid.s
  test/MC/Mips/mips64r6/invalid.s

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