[PATCH] D44370: [X86] Combine vXi64 multiplies to MULDQ/MULUDQ during DAG combine instead of lowering.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:15070
 
+  if (SDValue V = convertBuildVecZextToZext(N))
+    return V;
----------------
RKSimon wrote:
> Its strange that we have reduceBuildVecExtToExtBuildVec for post-legalization and this for pre-legalization. Not exactly the same I know.
I tried to enable reduceBuildVecExtToExtBuildVec pre-legalization, but it was too aggressive and caused many other issues. The first DAG combine effectively runs on the DAG bottom up. So we could fold BUILD_VECTORS of zero_extends before the zero_extends are combined with loads or truncates before them. So we would need to try to detect those opportunities and prevent the combine or add more combines to do the same combines with the new build_vector.


https://reviews.llvm.org/D44370