[llvm] r328713 - [AMDGPU][MC] Added ds_add_src2_f32

[Dmitry Preobrazhensky via llvm-commits]

Author: dpreobra
Date: Wed Mar 28 09:21:56 2018
New Revision: 328713

URL: http://llvm.org/viewvc/llvm-project?rev=328713&view=rev
Log:
[AMDGPU][MC] Added ds_add_src2_f32

See bug 36833: https://bugs.llvm.org/show_bug.cgi?id=36833

Differential Revision: https://reviews.llvm.org/D44779

Reviewers: arsenm, artem.tamazov, timcorringham

Modified:
    llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
    llvm/trunk/test/MC/AMDGPU/ds.s
    llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt

Modified: llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/DSInstructions.td?rev=328713&r1=328712&r2=328713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/DSInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/DSInstructions.td Wed Mar 28 09:21:56 2018
@@ -584,6 +584,8 @@ def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"
                                        int_amdgcn_ds_bpermute>;
 }
 
+def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
+
 } // let SubtargetPredicate = isVI
 
 //===----------------------------------------------------------------------===//
@@ -1129,6 +1131,7 @@ def DS_XOR_SRC2_B32_vi    : DS_Real_vi<0
 def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
 def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
 def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
+def DS_ADD_SRC2_F32_vi    : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
 def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
 def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
 def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;

Modified: llvm/trunk/test/MC/AMDGPU/ds.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/ds.s?rev=328713&r1=328712&r2=328713&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/ds.s (original)
+++ llvm/trunk/test/MC/AMDGPU/ds.s Wed Mar 28 09:21:56 2018
@@ -15,6 +15,14 @@ ds_add_u32 v2, v4 offset:16
 // SICI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
 // VI:   ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
 
+ds_add_src2_f32 v255 offset:65535
+// NOSICI: error
+// VI: ds_add_src2_f32 v255 offset:65535 ; encoding: [0xff,0xff,0x2a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_add_src2_f32 v0 offset:4 gds
+// NOSICI: error
+// VI: ds_add_src2_f32 v0 offset:4 gds ; encoding: [0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00]
+
 //===----------------------------------------------------------------------===//
 // Checks for 2 8-bit Offsets
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt?rev=328713&r1=328712&r2=328713&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt Wed Mar 28 09:21:56 2018
@@ -323,3 +323,6 @@
 
 # VI:   ds_read2st64_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xf0,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0xf0 0xd8 0x02 0x00 0x00 0x08
+
+# VI:   ds_add_src2_f32 v0 offset:4 gds ; encoding: [0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00]
+0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00