[PATCH] D44980: [MC][Tblgen] Allow the definition of processor register files in the scheduling model for llvm-mca

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: atrick, qcolombet, MatzeB, RKSimon, spatel, courbet.
Herald added subscribers: gbedwell, tschuett.

This patch allows the description of register files in processor scheduling models. This addresses PR36662.

A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td.

Targets can optionally describe register files for their processors using that class.
In particular, class RegisterFile allows to specify:

- the total number of physical registers.
- which target registers are accessible through the register file.
- the cost of allocating a register at register renaming stage.

Example (from this patch - see file `X86/X86ScheduleBtVer2.td`)

`  def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>`

Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar (btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM register definitions only cost 1 physical register.

The syntax allows to specify an empty set of register classes.
An empty set of register classes means: this register file models all the registers specified by the Target.
For each register class, users can specify an optional register cost. By default, register costs default to 1.
A value of  0 for the number of physical registers means: "this register file has an unbounded number of physical registers".

This patch is structured in two parts. The idea that each part can be committed separatedly.
I left the llvm-mca part here because it was easier to see the impact of the tablegen patch on tests.

Part 1 - MC/Tablegen
--------------------

A first part adds the tablegen definition of RegisterFile, and teaches the SubtargetEmitter how to emit information related to register files.

Information about register files is accessible through an instance of MCExtraProcessorInfo.
The idea behind this design is to logically partition the processor description which is only used by external tools (like llvm-mca) from the processor information used by the llvm machine schedulers.
I think that this design would make easier for targets to get rid of the extra processor information if they don't want it.

Part 2 - llvm-mca related
-------------------------

The second part of this patch is related to changes to llvm-mca.

The main differences are:

1. class RegisterFile now needs to take into account the "cost of a register" when allocating physical registers at register renaming stage.
2. Point 1. triggered a minor refactoring which lef to the removal of the "maximum 32 register files" restriction.
3. The BackendStatistics view has been updated so that we can print out extra details related to each register file implemented by the processor.

The effect of point 3. is also visible in tests register-files-[1..5].s.

Please let me know what you think.

Thanks,
Andrea


https://reviews.llvm.org/D44980

Files:
  include/llvm/MC/MCSchedule.h
  include/llvm/Target/TargetSchedule.td
  lib/Target/X86/X86ScheduleBtVer2.td
  test/tools/llvm-mca/X86/BtVer2/register-files-1.s
  test/tools/llvm-mca/X86/BtVer2/register-files-2.s
  test/tools/llvm-mca/X86/BtVer2/register-files-3.s
  test/tools/llvm-mca/X86/BtVer2/register-files-4.s
  test/tools/llvm-mca/X86/BtVer2/register-files-5.s
  tools/llvm-mca/Backend.h
  tools/llvm-mca/BackendStatistics.cpp
  tools/llvm-mca/BackendStatistics.h
  tools/llvm-mca/Dispatch.cpp
  tools/llvm-mca/Dispatch.h
  utils/TableGen/CodeGenSchedule.cpp
  utils/TableGen/CodeGenSchedule.h
  utils/TableGen/SubtargetEmitter.cpp

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