[PATCH] D44718: [AMDGPU] Define code object identification string used in AMDHSA runtimes.

[Tony Tye via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL328669: [AMDGPU] Define code object identification string used in AMDHSA runtimes. (authored by t-tye, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D44718?vs=139643&id=140003#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D44718

Files:
  llvm/trunk/docs/AMDGPUUsage.rst


Index: llvm/trunk/docs/AMDGPUUsage.rst
===================================================================
--- llvm/trunk/docs/AMDGPUUsage.rst
+++ llvm/trunk/docs/AMDGPUUsage.rst
@@ -910,6 +910,34 @@
 
 .. _amdgpu-amdhsa-hsa-code-object-metadata:
 
+Code Object Target Identification
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The AMDHSA OS uses the following syntax to specify the code object
+target as a single string:
+
+  ``<Architecture>-<Vendor>-<OS>-<Environment>-<Processor><Target Features>``
+
+Where:
+
+  - ``<Architecture>``, ``<Vendor>``, ``<OS>`` and ``<Environment>``
+    are the same as the *Target Triple* (see
+    :ref:`amdgpu-target-triples`).
+
+  - ``<Processor>`` is the same as the *Processor* (see
+    :ref:`amdgpu-processors`).
+
+  - ``<Target Features>`` is a list of the enabled *Target Features*
+    (see :ref:`amdgpu-target-features`), each prefixed by a plus, that
+    apply to *Processor*. The list must be in the same order as listed
+    in the table :ref:`amdgpu-target-feature-table`. Note that *Target
+    Features* must be included in the list if they are enabled even if
+    that is the default for *Processor*.
+
+For example:
+
+  ``"amdgcn-amd-amdhsa--gfx902+xnack"``
+
 Code Object Metadata
 ~~~~~~~~~~~~~~~~~~~~
 


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