[llvm] r328620 - [X86][Btver2] Add MMX_PMOVMSKBrr to MOVMSK scheduler class

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Mar 27 05:26:12 2018
New Revision: 328620

URL: http://llvm.org/viewvc/llvm-project?rev=328620&view=rev
Log:
[X86][Btver2] Add MMX_PMOVMSKBrr to MOVMSK scheduler class

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
    llvm/trunk/test/CodeGen/X86/mmx-schedule.ll

Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=328620&r1=328619&r2=328620&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Tue Mar 27 05:26:12 2018
@@ -776,7 +776,7 @@ def JWriteVMOVMSK: SchedWriteRes<[JFPU0,
 }
 def : InstRW<[JWriteVMOVMSK], (instrs MOVMSKPDrr, VMOVMSKPDrr, VMOVMSKPDYrr,
                                       MOVMSKPSrr, VMOVMSKPSrr, VMOVMSKPSYrr,
-                                      PMOVMSKBrr, VPMOVMSKBrr)>;
+                                      PMOVMSKBrr, VPMOVMSKBrr, MMX_PMOVMSKBrr)>;
 
 def JWriteVTESTY: SchedWriteRes<[JFPU01, JFPX, JFPA, JALU0]> {
   let Latency = 4;

Modified: llvm/trunk/test/CodeGen/X86/mmx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-schedule.ll?rev=328620&r1=328619&r2=328620&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mmx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mmx-schedule.ll Tue Mar 27 05:26:12 2018
@@ -4098,7 +4098,7 @@ define i32 @test_pmovmskb(x86_mmx %a0) o
 ;
 ; BTVER2-LABEL: test_pmovmskb:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    pmovmskb %mm0, %eax # sched: [1:0.50]
+; BTVER2-NEXT:    pmovmskb %mm0, %eax # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pmovmskb: