[PATCH] D43738: [X86] Use target independent zero_extend/sign_extend nodes for vectors with same number of elements.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Most of the code related to zero/sign_extend_vector_inreg is in the type legalizer. DAG combiner doesn't really do anything that cares about the rules. Not sure what the impact to other targets would be if we start messing with the legalization. Maybe we can keep type legalizing it the same way, but relax the rule. Then X86 would need to custom lower it to split?

I looked into just using extend_vector_inreg with 256 or 512 bit input types and then force an EXTRACT_SUBREG in the isel output patterns. But that failed when I couldn't represent (v64i32 (zero_extend_vector_inreg (v64i8))) on a non-BWI target since v64i8 isn't legal.


https://reviews.llvm.org/D43738