[llvm] r328574 - [Hexagon] Assertion failure in HexagonSubtarget.cpp
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 26 12:04:58 PDT 2018
Author: kparzysz
Date: Mon Mar 26 12:04:58 2018
New Revision: 328574
URL: http://llvm.org/viewvc/llvm-project?rev=328574&view=rev
Log:
[Hexagon] Assertion failure in HexagonSubtarget.cpp
In restoreLatency, replace range-for loop with std::find.
Patch by Jyotsna Verma.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=328574&r1=328573&r2=328574&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Mon Mar 26 12:04:58 2018
@@ -445,6 +445,7 @@ void HexagonSubtarget::restoreLatency(SU
}
assert(DefIdx >= 0 && "Def Reg not found in Src MI");
MachineInstr *DstI = Dst->getInstr();
+ SDep T = I;
for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
const MachineOperand &MO = DstI->getOperand(OpNum);
if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
@@ -461,11 +462,10 @@ void HexagonSubtarget::restoreLatency(SU
}
// Update the latency of opposite edge too.
- for (auto &J : Dst->Preds) {
- if (J.getSUnit() != Src)
- continue;
- J.setLatency(I.getLatency());
- }
+ T.setSUnit(Src);
+ auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
+ assert(F != Dst->Preds.end());
+ F->setLatency(I.getLatency());
}
}
@@ -473,7 +473,7 @@ void HexagonSubtarget::restoreLatency(SU
void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
const {
for (auto &I : Src->Succs) {
- if (I.getSUnit() != Dst)
+ if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
continue;
SDep T = I;
I.setLatency(Lat);
@@ -482,7 +482,7 @@ void HexagonSubtarget::changeLatency(SUn
T.setSUnit(Src);
auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
assert(F != Dst->Preds.end());
- F->setLatency(I.getLatency());
+ F->setLatency(Lat);
}
}
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