[llvm] r328551 - [X86][Btver2] Add CVTSI2SD/CVTSI2SS scheduler costs
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 26 10:02:02 PDT 2018
Author: rksimon
Date: Mon Mar 26 10:02:02 2018
New Revision: 328551
URL: http://llvm.org/viewvc/llvm-project?rev=328551&view=rev
Log:
[X86][Btver2] Add CVTSI2SD/CVTSI2SS scheduler costs
We still need to account for how Jaguar passes data from GPR -> XMM, which isn't as clean as XMM -> GPR.....
Modified:
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/test/CodeGen/X86/sse-schedule.ll
llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse1.s
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=328551&r1=328550&r2=328551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Mon Mar 26 10:02:02 2018
@@ -336,17 +336,30 @@ def JWriteCVTF2FLd : SchedWriteRes<[JLAG
}
def : InstRW<[JWriteCVTF2FLd], (instregex "(V)?CVTS(D|S)2S(D|S)rm")>;
-def JWriteCVTSI2F : SchedWriteRes<[JFPU1, JSTC, JFPA, JALU0]> {
+def JWriteCVTF2SI : SchedWriteRes<[JFPU1, JSTC, JFPA, JALU0]> {
let Latency = 7;
let NumMicroOps = 2;
}
-def : InstRW<[JWriteCVTSI2F], (instregex "(V)?CVT(T?)S(D|S)2SI(64)?rr")>;
+def : InstRW<[JWriteCVTF2SI], (instregex "(V)?CVT(T?)S(D|S)2SI(64)?rr")>;
-def JWriteCVTSI2FLd : SchedWriteRes<[JLAGU, JFPU1, JSTC, JFPA, JALU0]> {
+def JWriteCVTF2SILd : SchedWriteRes<[JLAGU, JFPU1, JSTC, JFPA, JALU0]> {
let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[JWriteCVTSI2FLd], (instregex "(V)?CVT(T?)S(D|S)2SI(64)?rm")>;
+def : InstRW<[JWriteCVTF2SILd], (instregex "(V)?CVT(T?)S(D|S)2SI(64)?rm")>;
+
+// FIXME: f+3 ST,LD+STC latency
+def JWriteCVTSI2F : SchedWriteRes<[JFPU1, JSTC]> {
+ let Latency = 9;
+ let NumMicroOps = 2;
+}
+def : InstRW<[JWriteCVTSI2F], (instregex "(V)?CVTSI(64)?2S(D|S)rr")>;
+
+def JWriteCVTSI2FLd : SchedWriteRes<[JLAGU, JFPU1, JSTC]> {
+ let Latency = 14;
+ let NumMicroOps = 2;
+}
+def : InstRW<[JWriteCVTSI2FLd], (instregex "(V)?CVTSI(64)?2S(D|S)rm")>;
////////////////////////////////////////////////////////////////////////////////
// Vector integer operations.
Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=328551&r1=328550&r2=328551&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Mon Mar 26 10:02:02 2018
@@ -1052,15 +1052,15 @@ define float @test_cvtsi2ss(i32 %a0, i32
;
; BTVER2-SSE-LABEL: test_cvtsi2ss:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: cvtsi2ssl (%rsi), %xmm0 # sched: [8:1.00]
-; BTVER2-SSE-NEXT: cvtsi2ssl %edi, %xmm1 # sched: [3:1.00]
+; BTVER2-SSE-NEXT: cvtsi2ssl (%rsi), %xmm0 # sched: [14:1.00]
+; BTVER2-SSE-NEXT: cvtsi2ssl %edi, %xmm1 # sched: [9:1.00]
; BTVER2-SSE-NEXT: addss %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_cvtsi2ss:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
+; BTVER2-NEXT: vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [9:1.00]
+; BTVER2-NEXT: vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
; BTVER2-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -1178,15 +1178,15 @@ define float @test_cvtsi2ssq(i64 %a0, i6
;
; BTVER2-SSE-LABEL: test_cvtsi2ssq:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: cvtsi2ssq (%rsi), %xmm0 # sched: [8:1.00]
-; BTVER2-SSE-NEXT: cvtsi2ssq %rdi, %xmm1 # sched: [3:1.00]
+; BTVER2-SSE-NEXT: cvtsi2ssq (%rsi), %xmm0 # sched: [14:1.00]
+; BTVER2-SSE-NEXT: cvtsi2ssq %rdi, %xmm1 # sched: [9:1.00]
; BTVER2-SSE-NEXT: addss %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_cvtsi2ssq:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
+; BTVER2-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [9:1.00]
+; BTVER2-NEXT: vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
; BTVER2-NEXT: vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=328551&r1=328550&r2=328551&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Mon Mar 26 10:02:02 2018
@@ -2348,15 +2348,15 @@ define double @test_cvtsi2sd(i32 %a0, i3
;
; BTVER2-SSE-LABEL: test_cvtsi2sd:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: cvtsi2sdl (%rsi), %xmm0 # sched: [8:1.00]
-; BTVER2-SSE-NEXT: cvtsi2sdl %edi, %xmm1 # sched: [3:1.00]
+; BTVER2-SSE-NEXT: cvtsi2sdl (%rsi), %xmm0 # sched: [14:1.00]
+; BTVER2-SSE-NEXT: cvtsi2sdl %edi, %xmm1 # sched: [9:1.00]
; BTVER2-SSE-NEXT: addsd %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_cvtsi2sd:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
+; BTVER2-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [9:1.00]
+; BTVER2-NEXT: vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -2474,15 +2474,15 @@ define double @test_cvtsi2sdq(i64 %a0, i
;
; BTVER2-SSE-LABEL: test_cvtsi2sdq:
; BTVER2-SSE: # %bb.0:
-; BTVER2-SSE-NEXT: cvtsi2sdq (%rsi), %xmm0 # sched: [8:1.00]
-; BTVER2-SSE-NEXT: cvtsi2sdq %rdi, %xmm1 # sched: [3:1.00]
+; BTVER2-SSE-NEXT: cvtsi2sdq (%rsi), %xmm0 # sched: [14:1.00]
+; BTVER2-SSE-NEXT: cvtsi2sdq %rdi, %xmm1 # sched: [9:1.00]
; BTVER2-SSE-NEXT: addsd %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_cvtsi2sdq:
; BTVER2: # %bb.0:
-; BTVER2-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
+; BTVER2-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [9:1.00]
+; BTVER2-NEXT: vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
; BTVER2-NEXT: vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse1.s?rev=328551&r1=328550&r2=328551&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse1.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-sse1.s Mon Mar 26 10:02:02 2018
@@ -158,10 +158,10 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 1 7 1.00 * cmpss $0, (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 comiss %xmm0, %xmm1
# CHECK-NEXT: 1 8 1.00 * comiss (%rax), %xmm1
-# CHECK-NEXT: 1 3 1.00 cvtsi2ssl %ecx, %xmm2
-# CHECK-NEXT: 1 3 1.00 cvtsi2ssq %rcx, %xmm2
-# CHECK-NEXT: 1 8 1.00 * cvtsi2ssl (%rax), %xmm2
-# CHECK-NEXT: 1 8 1.00 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 2 9 1.00 cvtsi2ssl %ecx, %xmm2
+# CHECK-NEXT: 2 9 1.00 cvtsi2ssq %rcx, %xmm2
+# CHECK-NEXT: 2 14 1.00 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 2 14 1.00 * cvtsi2ssl (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 cvtss2si %xmm0, %ecx
# CHECK-NEXT: 2 7 1.00 cvtss2si %xmm0, %rcx
# CHECK-NEXT: 2 12 1.00 * cvtss2si (%rax), %ecx
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