[llvm] r328496 - AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classes
Nicolai Haehnle via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 26 06:56:53 PDT 2018
Author: nha
Date: Mon Mar 26 06:56:53 2018
New Revision: 328496
URL: http://llvm.org/viewvc/llvm-project?rev=328496&view=rev
Log:
AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classes
Differential revision: https://reviews.llvm.org/D44820
Change-Id: I732979e2964006aa15d78a333d8886e6855f319a
Modified:
llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td
llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td
Modified: llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td?rev=328496&r1=328495&r2=328496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td Mon Mar 26 06:56:53 2018
@@ -19,17 +19,28 @@ def GPRIdxMode : Operand<i32> {
let OperandType = "OPERAND_IMMEDIATE";
}
+class SOP_Pseudo<string opName, dag outs, dag ins, string asmOps,
+ list<dag> pattern=[]> :
+ InstSI<outs, ins, "", pattern>,
+ SIMCInstr<opName, SIEncodingFamily.NONE> {
+
+ let isPseudo = 1;
+ let isCodeGenOnly = 1;
+ let SubtargetPredicate = isGCN;
+
+ string Mnemonic = opName;
+ string AsmOperands = asmOps;
+
+ bits<1> has_sdst = 0;
+}
+
//===----------------------------------------------------------------------===//
// SOP1 Instructions
//===----------------------------------------------------------------------===//
class SOP1_Pseudo <string opName, dag outs, dag ins,
string asmOps, list<dag> pattern=[]> :
- InstSI <outs, ins, "", pattern>,
- SIMCInstr<opName, SIEncodingFamily.NONE> {
- let isPseudo = 1;
- let isCodeGenOnly = 1;
- let SubtargetPredicate = isGCN;
+ SOP_Pseudo<opName, outs, ins, asmOps, pattern> {
let mayLoad = 0;
let mayStore = 0;
@@ -40,9 +51,6 @@ class SOP1_Pseudo <string opName, dag ou
let Size = 4;
let UseNamedOperandTable = 1;
- string Mnemonic = opName;
- string AsmOperands = asmOps;
-
bits<1> has_src0 = 1;
bits<1> has_sdst = 1;
}
@@ -253,11 +261,8 @@ def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set
class SOP2_Pseudo<string opName, dag outs, dag ins,
string asmOps, list<dag> pattern=[]> :
- InstSI<outs, ins, "", pattern>,
- SIMCInstr<opName, SIEncodingFamily.NONE> {
- let isPseudo = 1;
- let isCodeGenOnly = 1;
- let SubtargetPredicate = isGCN;
+ SOP_Pseudo<opName, outs, ins, asmOps, pattern> {
+
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -266,10 +271,7 @@ class SOP2_Pseudo<string opName, dag out
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
- string Mnemonic = opName;
- string AsmOperands = asmOps;
-
- bits<1> has_sdst = 1;
+ let has_sdst = 1;
// Pseudo instructions have no encodings, but adding this field here allows
// us to do:
@@ -279,7 +281,7 @@ class SOP2_Pseudo<string opName, dag out
// let Size = 4; // Do we need size here?
}
-class SOP2_Real<bits<7> op, SOP2_Pseudo ps> :
+class SOP2_Real<bits<7> op, SOP_Pseudo ps> :
InstSI <ps.OutOperandList, ps.InOperandList,
ps.Mnemonic # " " # ps.AsmOperands, []>,
Enc32 {
Modified: llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td?rev=328496&r1=328495&r2=328496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td Mon Mar 26 06:56:53 2018
@@ -40,17 +40,9 @@ class VOP1_SDWA9Ae <bits<8> op, VOPProfi
}
class VOP1_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], bit VOP1Only = 0> :
- InstSI <P.Outs32, P.Ins32, "", pattern>,
- VOP <opName>,
- SIMCInstr <!if(VOP1Only, opName, opName#"_e32"), SIEncodingFamily.NONE>,
- MnemonicAlias<!if(VOP1Only, opName, opName#"_e32"), opName> {
-
- let isPseudo = 1;
- let isCodeGenOnly = 1;
- let UseNamedOperandTable = 1;
+ VOP_Pseudo <opName, !if(VOP1Only, "", "_e32"), P, P.Outs32, P.Ins32, "", pattern> {
- string Mnemonic = opName;
- string AsmOperands = P.Asm32;
+ let AsmOperands = P.Asm32;
let Size = 4;
let mayLoad = 0;
@@ -63,8 +55,6 @@ class VOP1_Pseudo <string opName, VOPPro
let Uses = [EXEC];
let AsmVariantName = AMDGPUAsmVariants.Default;
-
- VOPProfile Pfl = P;
}
class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily> :
Modified: llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=328496&r1=328495&r2=328496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td Mon Mar 26 06:56:53 2018
@@ -61,17 +61,9 @@ class VOP2_SDWA9Ae <bits<6> op, VOPProfi
}
class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
- InstSI <P.Outs32, P.Ins32, "", pattern>,
- VOP <opName>,
- SIMCInstr <opName#suffix, SIEncodingFamily.NONE>,
- MnemonicAlias<opName#suffix, opName> {
-
- let isPseudo = 1;
- let isCodeGenOnly = 1;
- let UseNamedOperandTable = 1;
+ VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> {
- string Mnemonic = opName;
- string AsmOperands = P.Asm32;
+ let AsmOperands = P.Asm32;
let Size = 4;
let mayLoad = 0;
@@ -84,8 +76,6 @@ class VOP2_Pseudo <string opName, VOPPro
let Uses = [EXEC];
let AsmVariantName = AMDGPUAsmVariants.Default;
-
- VOPProfile Pfl = P;
}
class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
Modified: llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td?rev=328496&r1=328495&r2=328496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td Mon Mar 26 06:56:53 2018
@@ -718,9 +718,9 @@ multiclass VOP3Interp_F16_Real_gfx9<bits
}
multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
- def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
- VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
- VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
+ def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX9>,
+ VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl> {
+ VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME);
let AsmString = AsmName # ps.AsmOperands;
}
}
Modified: llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td?rev=328496&r1=328495&r2=328496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP3PInstructions.td Mon Mar 26 06:56:53 2018
@@ -144,8 +144,8 @@ def : GCNPat <
} // End SubtargetPredicate = [HasMadMixInsts]
multiclass VOP3P_Real_vi<bits<10> op> {
- def _vi : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.VI>,
- VOP3Pe <op, !cast<VOP3P_Pseudo>(NAME).Pfl> {
+ def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
+ VOP3Pe <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
let AssemblerPredicates = [HasVOP3PInsts];
let DecoderNamespace = "VI";
}
Modified: llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td?rev=328496&r1=328495&r2=328496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td Mon Mar 26 06:56:53 2018
@@ -38,6 +38,23 @@ class VOPAnyCommon <dag outs, dag ins, s
let Uses = [EXEC];
}
+class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins,
+ string asm, list<dag> pattern> :
+ InstSI <outs, ins, asm, pattern>,
+ VOP <opName>,
+ SIMCInstr <opName#suffix, SIEncodingFamily.NONE>,
+ MnemonicAlias<opName#suffix, opName> {
+
+ let isPseudo = 1;
+ let isCodeGenOnly = 1;
+ let UseNamedOperandTable = 1;
+
+ string Mnemonic = opName;
+ VOPProfile Pfl = P;
+
+ string AsmOperands;
+}
+
class VOP3Common <dag outs, dag ins, string asm = "",
list<dag> pattern = [], bit HasMods = 0,
bit VOP3Only = 0> :
@@ -66,26 +83,18 @@ class VOP3Common <dag outs, dag ins, str
class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
bit VOP3Only = 0, bit isVOP3P = 0, bit isVop3OpSel = 0> :
- InstSI <P.Outs64,
- !if(isVop3OpSel,
- P.InsVOP3OpSel,
- !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)),
- "",
- pattern>,
- VOP <opName>,
- SIMCInstr<opName#"_e64", SIEncodingFamily.NONE>,
- MnemonicAlias<opName#"_e64", opName> {
+ VOP_Pseudo <opName, "_e64", P, P.Outs64,
+ !if(isVop3OpSel,
+ P.InsVOP3OpSel,
+ !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)),
+ "", pattern> {
- let isPseudo = 1;
- let isCodeGenOnly = 1;
- let UseNamedOperandTable = 1;
let VOP3_OPSEL = isVop3OpSel;
let IsPacked = P.IsPacked;
- string Mnemonic = opName;
- string AsmOperands = !if(isVop3OpSel,
- P.AsmVOP3OpSel,
- !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64));
+ let AsmOperands = !if(isVop3OpSel,
+ P.AsmVOP3OpSel,
+ !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64));
let Size = 8;
let mayLoad = 0;
@@ -120,8 +129,6 @@ class VOP3_Pseudo <string opName, VOPPro
!if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
"cvtVOP3",
""));
-
- VOPProfile Pfl = P;
}
class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> :
@@ -129,7 +136,7 @@ class VOP3P_Pseudo <string opName, VOPPr
let VOP3P = 1;
}
-class VOP3_Real <VOP3_Pseudo ps, int EncodingFamily> :
+class VOP3_Real <VOP_Pseudo ps, int EncodingFamily> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
@@ -156,7 +163,7 @@ class VOP3_Real <VOP3_Pseudo ps, int Enc
// XXX - Is there any reason to distingusih this from regular VOP3
// here?
-class VOP3P_Real<VOP3P_Pseudo ps, int EncodingFamily> :
+class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily> :
VOP3_Real<ps, EncodingFamily>;
class VOP3a<VOPProfile P> : Enc64 {
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