[PATCH] D44843: [Power9]Legalize and emit code for quad-precision fma instructions

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:13755
   case MVT::f64:
+  case MVT::f128:
     return true;
----------------
This is only true if `Subtarget.hasP9Vector()`, so return that for the `f128` case.


================
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:2441
+  def XSMADDQP : X_VT5_VA5_VB5_FMA    <63, 388, "xsmaddqp"  ,
+                                   [(set f128:$vT,
+                                         (fma f128:$vA, f128:$vB, f128:$vTi))]>;
----------------
Something seems very wrong with the formatting here.


================
Comment at: test/CodeGen/PowerPC/f128-fma.ll:15
+; CHECK-NOT: bl fmal
+; CHECK: xsmaddqp
+; CHECK-NEXT: stxv
----------------
The order of operands here matters, so we'll need to be able to test which registers the values are loaded into so that the correct order of operands can be ensured with these FMA instructions.


https://reviews.llvm.org/D44843