[llvm] r328444 - [X86] Consistently prefix all defs in X86ScheduleSLM.td with 'SLM'.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 24 18:28:43 PDT 2018
Author: ctopper
Date: Sat Mar 24 18:28:43 2018
New Revision: 328444
URL: http://llvm.org/viewvc/llvm-project?rev=328444&view=rev
Log:
[X86] Consistently prefix all defs in X86ScheduleSLM.td with 'SLM'.
Modified:
llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=328444&r1=328443&r2=328444&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Sat Mar 24 18:28:43 2018
@@ -32,19 +32,19 @@ def SLMModel : SchedMachineModel {
let SchedModel = SLMModel in {
// Silvermont has 5 reservation stations for micro-ops
-def IEC_RSV0 : ProcResource<1>;
-def IEC_RSV1 : ProcResource<1>;
-def FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
-def FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
-def MEC_RSV : ProcResource<1>;
+def SLM_IEC_RSV0 : ProcResource<1>;
+def SLM_IEC_RSV1 : ProcResource<1>;
+def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
+def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
+def SLM_MEC_RSV : ProcResource<1>;
// Many micro-ops are capable of issuing on multiple ports.
-def IEC_RSV01 : ProcResGroup<[IEC_RSV0, IEC_RSV1]>;
-def FPC_RSV01 : ProcResGroup<[FPC_RSV0, FPC_RSV1]>;
+def SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>;
+def SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>;
-def SMDivider : ProcResource<1>;
-def SMFPMultiplier : ProcResource<1>;
-def SMFPDivider : ProcResource<1>;
+def SLMDivider : ProcResource<1>;
+def SLMFPMultiplier : ProcResource<1>;
+def SLMFPDivider : ProcResource<1>;
// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
// cycles after the memory operand.
@@ -55,9 +55,9 @@ def : ReadAdvance<ReadAfterLd, 3>;
// as two micro-ops when queued in the reservation station.
// This multiclass defines the resource usage for variants with and without
// folded loads.
-multiclass SMWriteResPair<X86FoldableSchedWrite SchedRW,
- list<ProcResourceKind> ExePorts,
- int Lat, list<int> Res = [1], int UOps = 1> {
+multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts,
+ int Lat, list<int> Res = [1], int UOps = 1> {
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
@@ -67,7 +67,7 @@ multiclass SMWriteResPair<X86FoldableSch
// Memory variant also uses a cycle on MEC_RSV and adds 3 cycles to the
// latency.
- def : WriteRes<SchedRW.Folded, !listconcat([MEC_RSV], ExePorts)> {
+ def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
let Latency = !add(Lat, 3);
let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = UOps;
@@ -76,165 +76,165 @@ multiclass SMWriteResPair<X86FoldableSch
// A folded store needs a cycle on MEC_RSV for the store data, but it does not
// need an extra port cycle to recompute the address.
-def : WriteRes<WriteRMW, [MEC_RSV]>;
+def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
-def : WriteRes<WriteStore, [IEC_RSV01, MEC_RSV]>;
-def : WriteRes<WriteLoad, [MEC_RSV]> { let Latency = 3; }
-def : WriteRes<WriteMove, [IEC_RSV01]>;
+def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
+def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; }
+def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
def : WriteRes<WriteZero, []>;
// Treat misc copies as a move.
def : InstRW<[WriteMove], (instrs COPY)>;
-defm : SMWriteResPair<WriteALU, [IEC_RSV01], 1>;
-defm : SMWriteResPair<WriteIMul, [IEC_RSV1], 3>;
-defm : SMWriteResPair<WriteShift, [IEC_RSV0], 1>;
-defm : SMWriteResPair<WriteJump, [IEC_RSV1], 1>;
+defm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>;
+defm : SLMWriteResPair<WriteIMul, [SLM_IEC_RSV1], 3>;
+defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>;
+defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on
// the port to read all inputs. We don't model that.
-def : WriteRes<WriteLEA, [IEC_RSV1]>;
+def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
// This is quite rough, latency depends on the dividend.
-def : WriteRes<WriteIDiv, [IEC_RSV01, SMDivider]> {
+def : WriteRes<WriteIDiv, [SLM_IEC_RSV01, SLMDivider]> {
let Latency = 25;
let ResourceCycles = [1, 25];
}
-def : WriteRes<WriteIDivLd, [MEC_RSV, IEC_RSV01, SMDivider]> {
+def : WriteRes<WriteIDivLd, [SLM_MEC_RSV, SLM_IEC_RSV01, SLMDivider]> {
let Latency = 29;
let ResourceCycles = [1, 1, 25];
}
// Scalar and vector floating point.
-def : WriteRes<WriteFStore, [FPC_RSV01, MEC_RSV]>;
-def : WriteRes<WriteFLoad, [MEC_RSV]> { let Latency = 3; }
-def : WriteRes<WriteFMove, [FPC_RSV01]>;
-
-defm : SMWriteResPair<WriteFAdd, [FPC_RSV1], 3>;
-defm : SMWriteResPair<WriteFMul, [FPC_RSV0, SMFPMultiplier], 5, [1,2]>;
-defm : SMWriteResPair<WriteFDiv, [FPC_RSV0, SMFPDivider], 34, [1,34]>;
-defm : SMWriteResPair<WriteFRcp, [FPC_RSV0], 5>;
-defm : SMWriteResPair<WriteFRsqrt, [FPC_RSV0], 5>;
-defm : SMWriteResPair<WriteFSqrt, [FPC_RSV0], 15>;
-defm : SMWriteResPair<WriteCvtF2I, [FPC_RSV01], 4>;
-defm : SMWriteResPair<WriteCvtI2F, [FPC_RSV01], 4>;
-defm : SMWriteResPair<WriteCvtF2F, [FPC_RSV01], 4>;
-defm : SMWriteResPair<WriteFShuffle, [FPC_RSV0], 1>;
-defm : SMWriteResPair<WriteFBlend, [FPC_RSV0], 1>;
+def : WriteRes<WriteFStore, [SLM_FPC_RSV01, SLM_MEC_RSV]>;
+def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; }
+def : WriteRes<WriteFMove, [SLM_FPC_RSV01]>;
+
+defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>;
+defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
+defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,34]>;
+defm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 5>;
+defm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 5>;
+defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0], 15>;
+defm : SLMWriteResPair<WriteCvtF2I, [SLM_FPC_RSV01], 4>;
+defm : SLMWriteResPair<WriteCvtI2F, [SLM_FPC_RSV01], 4>;
+defm : SLMWriteResPair<WriteCvtF2F, [SLM_FPC_RSV01], 4>;
+defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>;
// Vector integer operations.
-def : WriteRes<WriteVecStore, [FPC_RSV01, MEC_RSV]>;
-def : WriteRes<WriteVecLoad, [MEC_RSV]> { let Latency = 3; }
-def : WriteRes<WriteVecMove, [FPC_RSV01]>;
-
-defm : SMWriteResPair<WriteVecShift, [FPC_RSV0], 1>;
-defm : SMWriteResPair<WriteVecLogic, [FPC_RSV01], 1>;
-defm : SMWriteResPair<WriteVecALU, [FPC_RSV01], 1>;
-defm : SMWriteResPair<WriteVecIMul, [FPC_RSV0], 4>;
-defm : SMWriteResPair<WriteShuffle, [FPC_RSV0], 1>;
-defm : SMWriteResPair<WriteBlend, [FPC_RSV0], 1>;
-defm : SMWriteResPair<WriteMPSAD, [FPC_RSV0], 7>;
+def : WriteRes<WriteVecStore, [SLM_FPC_RSV01, SLM_MEC_RSV]>;
+def : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; }
+def : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>;
+
+defm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>;
+defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>;
+defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>;
+defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>;
////////////////////////////////////////////////////////////////////////////////
// Horizontal add/sub instructions.
////////////////////////////////////////////////////////////////////////////////
-defm : SMWriteResPair<WriteFHAdd, [FPC_RSV01], 3, [2]>;
-defm : SMWriteResPair<WritePHAdd, [FPC_RSV01], 1>;
+defm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV01], 3, [2]>;
+defm : SLMWriteResPair<WritePHAdd, [SLM_FPC_RSV01], 1>;
// String instructions.
// Packed Compare Implicit Length Strings, Return Mask
-def : WriteRes<WritePCmpIStrM, [FPC_RSV0]> {
+def : WriteRes<WritePCmpIStrM, [SLM_FPC_RSV0]> {
let Latency = 13;
let ResourceCycles = [13];
}
-def : WriteRes<WritePCmpIStrMLd, [FPC_RSV0, MEC_RSV]> {
+def : WriteRes<WritePCmpIStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 13;
let ResourceCycles = [13, 1];
}
// Packed Compare Explicit Length Strings, Return Mask
-def : WriteRes<WritePCmpEStrM, [FPC_RSV0]> {
+def : WriteRes<WritePCmpEStrM, [SLM_FPC_RSV0]> {
let Latency = 17;
let ResourceCycles = [17];
}
-def : WriteRes<WritePCmpEStrMLd, [FPC_RSV0, MEC_RSV]> {
+def : WriteRes<WritePCmpEStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 17;
let ResourceCycles = [17, 1];
}
// Packed Compare Implicit Length Strings, Return Index
-def : WriteRes<WritePCmpIStrI, [FPC_RSV0]> {
+def : WriteRes<WritePCmpIStrI, [SLM_FPC_RSV0]> {
let Latency = 17;
let ResourceCycles = [17];
}
-def : WriteRes<WritePCmpIStrILd, [FPC_RSV0, MEC_RSV]> {
+def : WriteRes<WritePCmpIStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 17;
let ResourceCycles = [17, 1];
}
// Packed Compare Explicit Length Strings, Return Index
-def : WriteRes<WritePCmpEStrI, [FPC_RSV0]> {
+def : WriteRes<WritePCmpEStrI, [SLM_FPC_RSV0]> {
let Latency = 21;
let ResourceCycles = [21];
}
-def : WriteRes<WritePCmpEStrILd, [FPC_RSV0, MEC_RSV]> {
+def : WriteRes<WritePCmpEStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 21;
let ResourceCycles = [21, 1];
}
// AES Instructions.
-def : WriteRes<WriteAESDecEnc, [FPC_RSV0]> {
+def : WriteRes<WriteAESDecEnc, [SLM_FPC_RSV0]> {
let Latency = 8;
let ResourceCycles = [5];
}
-def : WriteRes<WriteAESDecEncLd, [FPC_RSV0, MEC_RSV]> {
+def : WriteRes<WriteAESDecEncLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 8;
let ResourceCycles = [5, 1];
}
-def : WriteRes<WriteAESIMC, [FPC_RSV0]> {
+def : WriteRes<WriteAESIMC, [SLM_FPC_RSV0]> {
let Latency = 8;
let ResourceCycles = [5];
}
-def : WriteRes<WriteAESIMCLd, [FPC_RSV0, MEC_RSV]> {
+def : WriteRes<WriteAESIMCLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 8;
let ResourceCycles = [5, 1];
}
-def : WriteRes<WriteAESKeyGen, [FPC_RSV0]> {
+def : WriteRes<WriteAESKeyGen, [SLM_FPC_RSV0]> {
let Latency = 8;
let ResourceCycles = [5];
}
-def : WriteRes<WriteAESKeyGenLd, [FPC_RSV0, MEC_RSV]> {
+def : WriteRes<WriteAESKeyGenLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 8;
let ResourceCycles = [5, 1];
}
// Carry-less multiplication instructions.
-def : WriteRes<WriteCLMul, [FPC_RSV0]> {
+def : WriteRes<WriteCLMul, [SLM_FPC_RSV0]> {
let Latency = 10;
let ResourceCycles = [10];
}
-def : WriteRes<WriteCLMulLd, [FPC_RSV0, MEC_RSV]> {
+def : WriteRes<WriteCLMulLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 10;
let ResourceCycles = [10, 1];
}
-def : WriteRes<WriteSystem, [FPC_RSV0]> { let Latency = 100; }
-def : WriteRes<WriteMicrocoded, [FPC_RSV0]> { let Latency = 100; }
-def : WriteRes<WriteFence, [MEC_RSV]>;
+def : WriteRes<WriteSystem, [SLM_FPC_RSV0]> { let Latency = 100; }
+def : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; }
+def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
def : WriteRes<WriteNop, []>;
// AVX/FMA is not supported on that architecture, but we should define the basic
// scheduling resources anyway.
-def : WriteRes<WriteIMulH, [FPC_RSV0]>;
-defm : SMWriteResPair<WriteVarBlend, [FPC_RSV0], 1>;
-defm : SMWriteResPair<WriteFVarBlend, [FPC_RSV0], 1>;
-defm : SMWriteResPair<WriteFShuffle256, [FPC_RSV0], 1>;
-defm : SMWriteResPair<WriteShuffle256, [FPC_RSV0], 1>;
-defm : SMWriteResPair<WriteVarVecShift, [FPC_RSV0], 1>;
-defm : SMWriteResPair<WriteFMA, [FPC_RSV0], 1>;
+def : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>;
+defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteFShuffle256, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteShuffle256, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteFMA, [SLM_FPC_RSV0], 1>;
} // SchedModel
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