[PATCH] D44849: AMDGPU: Fix FP restore from being reordered with stack ops
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 23 15:30:01 PDT 2018
arsenm created this revision.
arsenm added a reviewer: rampitec.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.
In a function, s5 is used as the frame base SGPR. Before it was
possible if there were stack operations immediately after
the call to be moved before the FP restore copy after the call.
I'm not 100% satisfied with the solution of adding an implicit
use to the ADJCALLSTACK* pseudo, but I'm not sure what would
be better.
https://reviews.llvm.org/D44849
Files:
lib/Target/AMDGPU/SIISelLowering.cpp
test/CodeGen/AMDGPU/call-preserved-registers.ll
Index: test/CodeGen/AMDGPU/call-preserved-registers.ll
===================================================================
--- test/CodeGen/AMDGPU/call-preserved-registers.ll
+++ test/CodeGen/AMDGPU/call-preserved-registers.ll
@@ -34,9 +34,9 @@
; GCN: s_mov_b32 s33, s5
; GCN-NEXT: s_swappc_b64
; GCN-NEXT: s_mov_b32 s5, s33
+; GCN-NEXT: s_mov_b32 s33, s5
; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ;;#ASMEND
-; GCN-NEXT: s_mov_b32 s33, s5
; GCN-NEXT: s_swappc_b64
; GCN-NEXT: s_mov_b32 s5, s33
; GCN: v_readlane_b32 s37, v32, 4
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3351,8 +3351,13 @@
case AMDGPU::ADJCALLSTACKDOWN: {
const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
MachineInstrBuilder MIB(*MF, &MI);
+
+ // Add an implicit use of the frame offset reg to prevent the restore copy
+ // inserted after the call from being reorderd after stack operations in the
+ // the caller's frame.
MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
- .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit);
+ .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
+ .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
return BB;
}
case AMDGPU::SI_CALL_ISEL:
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