[PATCH] D44841: [X86][Znver1] Remove InstRWs for BLENDVPS/PD
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 23 14:56:41 PDT 2018
RKSimon added a comment.
In https://reviews.llvm.org/D44841#1047129, @craig.topper wrote:
> Why can't just explicitly set the sse level?
Yes, I can - it does mean that we'll lose VEX coverage for a lot of instructions - we can either add 2 entries for each target or I add tests to avx/avx2-schedule.
There are a few cost diffs (e.g. sandybridge cvtss2sirm is different to vcvtss2sirm).
https://reviews.llvm.org/D44841
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