[PATCH] D44841: [X86][Znver1] Remove InstRWs for BLENDVPS/PD

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

> The patterns were missing the VEX forms which is why there are no test changes. We don't test "-mcpu=znver1 -mattr=-avx"

Thanks for reminding me - we need to fix the sse schedule tests to not use the vex instructions. I'll look at replacing then with inline asm.


https://reviews.llvm.org/D44841