[llvm] r328355 - [Hexagon] Fold offset in base+immediate loads/stores
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 23 12:30:34 PDT 2018
Author: kparzysz
Date: Fri Mar 23 12:30:34 2018
New Revision: 328355
URL: http://llvm.org/viewvc/llvm-project?rev=328355&view=rev
Log:
[Hexagon] Fold offset in base+immediate loads/stores
Optimize Ry = add(Rx,#n); memw(Ry+#0) = Rz => memw(Rx,#n) = Rz.
Patch by Jyotsna Verma.
Added:
llvm/trunk/test/CodeGen/Hexagon/addr-mode-opt.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp?rev=328355&r1=328354&r2=328355&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp Fri Mar 23 12:30:34 2018
@@ -27,6 +27,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
@@ -78,7 +79,9 @@ private:
using MISetType = DenseSet<MachineInstr *>;
using InstrEvalMap = DenseMap<MachineInstr *, bool>;
+ MachineRegisterInfo *MRI = nullptr;
const HexagonInstrInfo *HII = nullptr;
+ const HexagonRegisterInfo *HRI = nullptr;
MachineDominatorTree *MDT = nullptr;
DataFlowGraph *DFG = nullptr;
DataFlowGraph::DefStackMap DefM;
@@ -88,11 +91,16 @@ private:
bool processBlock(NodeAddr<BlockNode *> BA);
bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
NodeAddr<UseNode *> UseN, unsigned UseMOnum);
+ bool processAddUses(NodeAddr<StmtNode *> AddSN, MachineInstr *AddMI,
+ const NodeList &UNodeList);
+ bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI);
bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
InstrEvalMap &InstrEvalResult, short &SizeInc);
bool hasRepForm(MachineInstr &MI, unsigned TfrDefR);
bool canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN, MachineInstr &MI,
const NodeList &UNodeList);
+ bool isSafeToExtLR(NodeAddr<StmtNode *> SN, MachineInstr *MI,
+ unsigned LRExtReg, const NodeList &UNodeList);
void getAllRealUses(NodeAddr<StmtNode *> SN, NodeList &UNodeList);
bool allValidCandidates(NodeAddr<StmtNode *> SA, NodeList &UNodeList);
short getBaseWithLongOffset(const MachineInstr &MI) const;
@@ -101,6 +109,7 @@ private:
bool changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, unsigned ImmOpNum);
bool changeAddAsl(NodeAddr<UseNode *> AddAslUN, MachineInstr *AddAslMI,
const MachineOperand &ImmOp, unsigned ImmOpNum);
+ bool isValidOffset(MachineInstr *MI, int Offset);
};
} // end anonymous namespace
@@ -272,6 +281,152 @@ void HexagonOptAddrMode::getAllRealUses(
}
}
+bool HexagonOptAddrMode::isSafeToExtLR(NodeAddr<StmtNode *> SN,
+ MachineInstr *MI, unsigned LRExtReg,
+ const NodeList &UNodeList) {
+ RegisterRef LRExtRR;
+ NodeId LRExtRegRD = 0;
+ // Iterate through all the UseNodes in SN and find the reaching def
+ // for the LRExtReg.
+ for (NodeAddr<UseNode *> UA : SN.Addr->members_if(DFG->IsUse, *DFG)) {
+ RegisterRef RR = UA.Addr->getRegRef(*DFG);
+ if (LRExtReg == RR.Reg) {
+ LRExtRR = RR;
+ LRExtRegRD = UA.Addr->getReachingDef();
+ }
+ }
+
+ for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
+ NodeAddr<UseNode *> UA = *I;
+ NodeAddr<InstrNode *> IA = UA.Addr->getOwner(*DFG);
+ // The reaching def of LRExtRR at load/store node should be same as the
+ // one reaching at the SN.
+ if (UA.Addr->getFlags() & NodeAttrs::PhiRef)
+ return false;
+ NodeAddr<RefNode*> AA = LV->getNearestAliasedRef(LRExtRR, IA);
+ if ((DFG->IsDef(AA) && AA.Id != LRExtRegRD) ||
+ AA.Addr->getReachingDef() != LRExtRegRD) {
+ DEBUG(dbgs() << "isSafeToExtLR: Returning false; another reaching def\n");
+ return false;
+ }
+
+ MachineInstr *UseMI = NodeAddr<StmtNode *>(IA).Addr->getCode();
+ NodeAddr<DefNode *> LRExtRegDN = DFG->addr<DefNode *>(LRExtRegRD);
+ // Reaching Def to LRExtReg can't be a phi.
+ if ((LRExtRegDN.Addr->getFlags() & NodeAttrs::PhiRef) &&
+ MI->getParent() != UseMI->getParent())
+ return false;
+ }
+ return true;
+}
+
+bool HexagonOptAddrMode::isValidOffset(MachineInstr *MI, int Offset) {
+ unsigned AlignMask = 0;
+ switch (HII->getMemAccessSize(*MI)) {
+ case HexagonII::MemAccessSize::DoubleWordAccess:
+ AlignMask = 0x7;
+ break;
+ case HexagonII::MemAccessSize::WordAccess:
+ AlignMask = 0x3;
+ break;
+ case HexagonII::MemAccessSize::HalfWordAccess:
+ AlignMask = 0x1;
+ break;
+ case HexagonII::MemAccessSize::ByteAccess:
+ AlignMask = 0x0;
+ break;
+ default:
+ return false;
+ }
+
+ if ((AlignMask & Offset) != 0)
+ return false;
+ return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false);
+}
+
+bool HexagonOptAddrMode::processAddUses(NodeAddr<StmtNode *> AddSN,
+ MachineInstr *AddMI,
+ const NodeList &UNodeList) {
+
+ unsigned AddDefR = AddMI->getOperand(0).getReg();
+ for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
+ NodeAddr<UseNode *> UN = *I;
+ NodeAddr<StmtNode *> SN = UN.Addr->getOwner(*DFG);
+ MachineInstr *MI = SN.Addr->getCode();
+ const MCInstrDesc &MID = MI->getDesc();
+ if ((!MID.mayLoad() && !MID.mayStore()) ||
+ HII->getAddrMode(*MI) != HexagonII::BaseImmOffset ||
+ HII->isHVXVec(*MI))
+ return false;
+
+ MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1)
+ : MI->getOperand(0);
+
+ if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR)
+ return false;
+
+ MachineOperand OffsetOp = MID.mayLoad() ? MI->getOperand(2)
+ : MI->getOperand(1);
+ if (!OffsetOp.isImm())
+ return false;
+
+ int64_t newOffset = OffsetOp.getImm() + AddMI->getOperand(2).getImm();
+ if (!isValidOffset(MI, newOffset))
+ return false;
+
+ // Since we'll be extending the live range of Rt in the following example,
+ // make sure that is safe. another definition of Rt doesn't exist between 'add'
+ // and load/store instruction.
+ //
+ // Ex: Rx= add(Rt,#10)
+ // memw(Rx+#0) = Rs
+ // will be replaced with => memw(Rt+#10) = Rs
+ unsigned BaseReg = AddMI->getOperand(1).getReg();
+ if (!isSafeToExtLR(AddSN, AddMI, BaseReg, UNodeList))
+ return false;
+ }
+
+ // Update all the uses of 'add' with the appropriate base and offset
+ // values.
+ bool Changed = false;
+ for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
+ NodeAddr<UseNode *> UseN = *I;
+ assert(!(UseN.Addr->getFlags() & NodeAttrs::PhiRef) &&
+ "Found a PhiRef node as a real reached use!!");
+
+ NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG);
+ MachineInstr *UseMI = OwnerN.Addr->getCode();
+ unsigned BBNum = UseMI->getParent()->getNumber();
+ DEBUG(dbgs() << "\t\t[MI <BB#" << BBNum << ">]: " << *UseMI << "\n");
+ Changed |= updateAddUses(AddMI, UseMI);
+ }
+
+ if (Changed)
+ Deleted.insert(AddMI);
+
+ return Changed;
+}
+
+bool HexagonOptAddrMode::updateAddUses(MachineInstr *AddMI,
+ MachineInstr *UseMI) {
+ const MachineOperand ImmOp = AddMI->getOperand(2);
+ const MachineOperand AddRegOp = AddMI->getOperand(1);
+ unsigned newReg = AddRegOp.getReg();
+ const MCInstrDesc &MID = UseMI->getDesc();
+
+ MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1)
+ : UseMI->getOperand(0);
+ MachineOperand &OffsetOp = MID.mayLoad() ? UseMI->getOperand(2)
+ : UseMI->getOperand(1);
+ BaseOp.setReg(newReg);
+ BaseOp.setIsUndef(AddRegOp.isUndef());
+ BaseOp.setImplicit(AddRegOp.isImplicit());
+ OffsetOp.setImm(ImmOp.getImm() + OffsetOp.getImm());
+ MRI->clearKillFlags(newReg);
+
+ return true;
+}
+
bool HexagonOptAddrMode::analyzeUses(unsigned tfrDefR,
const NodeList &UNodeList,
InstrEvalMap &InstrEvalResult,
@@ -534,9 +689,11 @@ bool HexagonOptAddrMode::processBlock(No
NodeAddr<StmtNode *> SA = IA;
MachineInstr *MI = SA.Addr->getCode();
- if (MI->getOpcode() != Hexagon::A2_tfrsi ||
- !MI->getOperand(1).isGlobal())
- continue;
+ if ((MI->getOpcode() != Hexagon::A2_tfrsi ||
+ !MI->getOperand(1).isGlobal()) &&
+ (MI->getOpcode() != Hexagon::A2_addi ||
+ !MI->getOperand(2).isImm() || HII->isConstExtended(*MI)))
+ continue;
DEBUG(dbgs() << "[Analyzing " << HII->getName(MI->getOpcode()) << "]: "
<< *MI << "\n\t[InstrNode]: "
@@ -548,6 +705,21 @@ bool HexagonOptAddrMode::processBlock(No
if (!allValidCandidates(SA, UNodeList))
continue;
+ // Analyze all uses of 'add'. If the output of 'add' is used as an address
+ // in the base+immediate addressing mode load/store instructions, see if
+ // they can be updated to use the immediate value as an offet. Thus,
+ // providing us the opportunity to eliminate 'add'.
+ // Ex: Rx= add(Rt,#12)
+ // memw(Rx+#0) = Rs
+ // This can be replaced with memw(Rt+#12) = Rs
+ //
+ // This transformation is only performed if all uses can be updated and
+ // the offset isn't required to be constant extended.
+ if (MI->getOpcode() == Hexagon::A2_addi) {
+ Changed |= processAddUses(SA, MI, UNodeList);
+ continue;
+ }
+
short SizeInc = 0;
unsigned DefR = MI->getOperand(0).getReg();
InstrEvalMap InstrEvalResult;
@@ -580,9 +752,11 @@ bool HexagonOptAddrMode::processBlock(No
if (op.isReg() && op.isUse() && DefR == op.getReg())
UseMOnum = j;
}
- assert(UseMOnum >= 0 && "Invalid reached use!");
+ // It is possible that the register will not be found in any operand.
+ // This could happen, for example, when DefR = R4, but the used
+ // register is D2.
- if (InstrEvalResult[UseMI])
+ if (UseMOnum >= 0 && InstrEvalResult[UseMI])
// Change UseMI if replacement is possible.
Changed |= xformUseMI(MI, UseMI, UseN, UseMOnum);
else
@@ -600,20 +774,20 @@ bool HexagonOptAddrMode::runOnMachineFun
bool Changed = false;
auto &HST = MF.getSubtarget<HexagonSubtarget>();
- auto &MRI = MF.getRegInfo();
+ MRI = &MF.getRegInfo();
HII = HST.getInstrInfo();
+ HRI = HST.getRegisterInfo();
const auto &MDF = getAnalysis<MachineDominanceFrontier>();
MDT = &getAnalysis<MachineDominatorTree>();
- const auto &TRI = *MF.getSubtarget().getRegisterInfo();
const TargetOperandInfo TOI(*HII);
- DataFlowGraph G(MF, *HII, TRI, *MDT, MDF, TOI);
+ DataFlowGraph G(MF, *HII, *HRI, *MDT, MDF, TOI);
// Need to keep dead phis because we can propagate uses of registers into
// nodes dominated by those would-be phis.
G.build(BuildOptions::KeepDeadPhis);
DFG = &G;
- Liveness L(MRI, *DFG);
+ Liveness L(*MRI, *DFG);
L.computePhiInfo();
LV = &L;
Added: llvm/trunk/test/CodeGen/Hexagon/addr-mode-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addr-mode-opt.ll?rev=328355&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addr-mode-opt.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/addr-mode-opt.ll Fri Mar 23 12:30:34 2018
@@ -0,0 +1,55 @@
+; Broken by r326208
+; XFAIL: *
+; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
+; CHECK-NOT: add(r{{[0-9]+}},#2)
+; CHECK-NOT: add(r{{[0-9]+}},#3)
+; CHECK: memub(r{{[0-9]+}}+#2)
+; CHECK: memub(r{{[0-9]+}}+#3)
+
+ at g0 = external global i32, align 4
+
+define i32 @f0(i8* nocapture readonly %a0, i8* nocapture readonly %a1) {
+b0:
+ %v0 = getelementptr inbounds i8, i8* %a0, i32 2
+ %v1 = getelementptr inbounds i8, i8* %a1, i32 3
+ br label %b2
+
+b1: ; preds = %b3
+ %v2 = getelementptr inbounds i8, i8* %a0, i32 %v7
+ %v3 = add nuw nsw i32 %v7, 1
+ %v4 = getelementptr inbounds i8, i8* %a1, i32 %v3
+ %v5 = icmp eq i32 %v7, 3
+ br i1 %v5, label %b4, label %b2
+
+b2: ; preds = %b1, %b0
+ %v6 = phi i8* [ %v1, %b0 ], [ %v4, %b1 ]
+ %v7 = phi i32 [ 3, %b0 ], [ %v3, %b1 ]
+ %v8 = phi i8* [ %v0, %b0 ], [ %v2, %b1 ]
+ br label %b3
+
+b3: ; preds = %b3, %b2
+ %v9 = load i8, i8* %v8, align 1
+ %v10 = zext i8 %v9 to i32
+ %v11 = load i8, i8* %v6, align 1
+ %v12 = zext i8 %v11 to i32
+ %v13 = tail call i32 bitcast (i32 (...)* @f1 to i32 (i32, i32)*)(i32 %v10, i32 %v12)
+ %v14 = icmp eq i32 %v13, 0
+ br i1 %v14, label %b1, label %b3
+
+b4: ; preds = %b1
+ %v15 = tail call i32 @f2(i8* %a0, i8* %a1)
+ %v16 = icmp sgt i32 %v15, 0
+ br i1 %v16, label %b5, label %b6
+
+b5: ; preds = %b4
+ store i32 10, i32* @g0, align 4
+ br label %b6
+
+b6: ; preds = %b5, %b4
+ %v17 = phi i32 [ 1, %b5 ], [ 0, %b4 ]
+ ret i32 %v17
+}
+
+declare i32 @f1(...)
+
+declare i32 @f2(i8* nocapture, i8* nocapture)
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