[llvm] r328275 - [TableGen] Don't capture returned std::vectors by const reference.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 22 17:02:45 PDT 2018
Author: ctopper
Date: Thu Mar 22 17:02:45 2018
New Revision: 328275
URL: http://llvm.org/viewvc/llvm-project?rev=328275&view=rev
Log:
[TableGen] Don't capture returned std::vectors by const reference.
The full vector is being returned not a reference. So the reference was just a to a temporary.
Modified:
llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=328275&r1=328274&r2=328275&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Thu Mar 22 17:02:45 2018
@@ -194,8 +194,7 @@ unsigned SubtargetEmitter::FeatureKeyVal
<< "\"" << Desc << "\", "
<< "{ " << Target << "::" << Name << " }, ";
- const std::vector<Record*> &ImpliesList =
- Feature->getValueAsListOfDefs("Implies");
+ RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies");
OS << "{";
for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
@@ -230,8 +229,7 @@ unsigned SubtargetEmitter::CPUKeyValues(
// For each processor
for (Record *Processor : ProcessorList) {
StringRef Name = Processor->getValueAsString("Name");
- const std::vector<Record*> &FeatureList =
- Processor->getValueAsListOfDefs("Features");
+ RecVec FeatureList = Processor->getValueAsListOfDefs("Features");
// Emit as { "cpu", "description", { f1 , f2 , ... fn } },
OS << " { "
@@ -263,8 +261,7 @@ void SubtargetEmitter::FormItineraryStag
std::string &ItinString,
unsigned &NStages) {
// Get states list
- const std::vector<Record*> &StageList =
- ItinData->getValueAsListOfDefs("Stages");
+ RecVec StageList = ItinData->getValueAsListOfDefs("Stages");
// For each stage
unsigned N = NStages = StageList.size();
@@ -277,7 +274,7 @@ void SubtargetEmitter::FormItineraryStag
ItinString += " { " + itostr(Cycles) + ", ";
// Get unit list
- const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
+ RecVec UnitList = Stage->getValueAsListOfDefs("Units");
// For each unit
for (unsigned j = 0, M = UnitList.size(); j < M;) {
@@ -306,7 +303,7 @@ void SubtargetEmitter::FormItineraryStag
void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
std::string &ItinString, unsigned &NOperandCycles) {
// Get operand cycle list
- const std::vector<int64_t> &OperandCycleList =
+ std::vector<int64_t> OperandCycleList =
ItinData->getValueAsListOfInts("OperandCycles");
// For each operand cycle
@@ -324,8 +321,7 @@ void SubtargetEmitter::FormItineraryBypa
Record *ItinData,
std::string &ItinString,
unsigned NOperandCycles) {
- const std::vector<Record*> &BypassList =
- ItinData->getValueAsListOfDefs("Bypasses");
+ RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses");
unsigned N = BypassList.size();
unsigned i = 0;
for (; i < N;) {
@@ -356,7 +352,7 @@ EmitStageAndOperandCycleData(raw_ostream
if (!ItinsDefSet.insert(ProcModel.ItinsDef).second)
continue;
- std::vector<Record*> FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");
+ RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");
if (FUs.empty())
continue;
@@ -370,7 +366,7 @@ EmitStageAndOperandCycleData(raw_ostream
OS << "} // end namespace " << Name << "FU\n";
- std::vector<Record*> BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
+ RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
if (!BPs.empty()) {
OS << "\n// Pipeline forwarding paths for itineraries \"" << Name
<< "\"\n" << "namespace " << Name << "Bypass {\n";
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