[PATCH] D44794: [AArch64] Don't reduce the width of loads if it prevents combining a shift

[John Brawn via Phabricator via llvm-commits]

john.brawn created this revision.
john.brawn added reviewers: t.p.northover, mstorsjo, sebpop, olista01.
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar, rengolin.

Loads and stores can only shift the offset register by the size of the value being loaded, but currently the DAGCombiner will reduce the width of the load if it's followed by a trunc making it impossible to later combine the shift.

Solve this by implementing shouldReduceLoadWidth for the AArch64 backend and make it prevent the width reduction if this is what would happen, though do allow it if reducing the load width will let us eliminate a later sign or zero extend.


Repository:
  rL LLVM

https://reviews.llvm.org/D44794

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  test/CodeGen/AArch64/arm64-fold-lsl.ll
  test/CodeGen/AArch64/arm64-register-offset-addressing.ll

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