[PATCH] D41949: [RISCV] implement li pseudo instruction

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

Thanks Mario. I think this is looking good to land now.

Are you planning a follow-up patch that will show `li` in disassembly and for generated assembly in simple cases? (matching binutils more closely).

I haven't looked into it more closely, but I do note a minor codegen change for float-mem.ll which results in an extra instruction:

   ; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
   define float @flw_fsw_constant(float %a) nounwind {
   ; RV32IF-LABEL: flw_fsw_constant:
   ; RV32IF:       # %bb.0:
   ; RV32IF-NEXT:    fmv.w.x ft0, a0
   ; RV32IF-NEXT:    lui a0, 912092
  -; RV32IF-NEXT:    flw ft1, -273(a0)
  +; RV32IF-NEXT:    addi a0, a0, -273
  +; RV32IF-NEXT:    flw ft1, 0(a0)
   ; RV32IF-NEXT:    fadd.s ft0, ft0, ft1
  -; RV32IF-NEXT:    fsw ft0, -273(a0)
  +; RV32IF-NEXT:    fsw ft0, 0(a0)
   ; RV32IF-NEXT:    fmv.x.w a0, ft0
   ; RV32IF-NEXT:    ret
     %1 = inttoptr i32 3735928559 to float*
     %2 = load volatile float, float* %1
     %3 = fadd float %a, %2
     store float %3, float* %1
     ret float %3
   }


https://reviews.llvm.org/D41949