Author: rksimon
Date: Wed Mar 21 09:05:58 2018
New Revision: 328110
URL: http://llvm.org/viewvc/llvm-project?rev=328110&view=rev
Log:
[X86][SandyBridge] Merge more VEX/non-VEX instregex patterns (NFCI) (PR35955)
Modified:
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=328110&r1=328109&r2=328110&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Wed Mar 21 09:05:58 2018
@@ -255,25 +255,16 @@ def SBWriteResGroup0 : SchedWriteRes<[SB
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup0], (instregex "CVTSS2SDrr",
- "PSLLDri",
- "PSLLQri",
- "PSLLWri",
- "PSRADri",
- "PSRAWri",
- "PSRLDri",
- "PSRLQri",
- "PSRLWri",
- "VCVTSS2SDrr",
- "VPMOVMSKBrr",
- "VPSLLDri",
- "VPSLLQri",
- "VPSLLWri",
- "VPSRADri",
- "VPSRAWri",
- "VPSRLDri",
- "VPSRLQri",
- "VPSRLWri",
+def: InstRW<[SBWriteResGroup0], (instregex "VPMOVMSKBrr",
+ "(V?)CVTSS2SDrr",
+ "(V?)PSLLDri",
+ "(V?)PSLLQri",
+ "(V?)PSLLWri",
+ "(V?)PSRADri",
+ "(V?)PSRAWri",
+ "(V?)PSRLDri",
+ "(V?)PSRLQri",
+ "(V?)PSRLWri",
"VTESTPDYrr",
"VTESTPDrr",
"VTESTPSYrr",
@@ -295,11 +286,7 @@ def SBWriteResGroup2 : SchedWriteRes<[SB
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>;
-def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr",
- "ANDNPSrr",
- "ANDPDrr",
- "ANDPSrr",
- "FDECSTP",
+def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP",
"FFREE",
"FINCSTP",
"FNOP",
@@ -310,65 +297,44 @@ def: InstRW<[SBWriteResGroup2], (instreg
"JMP_1",
"JMP_4",
"LD_Frr",
- "MOV64toPQIrr",
- "MOVAPDrr",
- "MOVAPSrr",
- "MOVDDUPrr",
- "MOVDI2PDIrr",
- "MOVHLPSrr",
- "MOVLHPSrr",
- "MOVSDrr",
- "MOVSHDUPrr",
- "MOVSLDUPrr",
- "MOVSSrr",
- "MOVUPDrr",
- "MOVUPSrr",
- "ORPDrr",
- "ORPSrr",
"RETQ",
- "SHUFPDrri",
- "SHUFPSrri",
"ST_FPrr",
"ST_Frr",
- "UNPCKHPDrr",
- "UNPCKHPSrr",
- "UNPCKLPDrr",
- "UNPCKLPSrr",
"VANDNPDYrr",
- "VANDNPDrr",
+ "(V?)ANDNPDrr",
"VANDNPSYrr",
- "VANDNPSrr",
+ "(V?)ANDNPSrr",
"VANDPDYrr",
- "VANDPDrr",
+ "(V?)ANDPDrr",
"VANDPSYrr",
- "VANDPSrr",
+ "(V?)ANDPSrr",
"VEXTRACTF128rr",
"VINSERTF128rr",
"VINSERTPSrr",
- "VMOV64toPQIrr",
+ "(V?)MOV64toPQIrr",
"VMOVAPDYrr",
- "VMOVAPDrr",
+ "(V?)MOVAPDrr",
"VMOVAPSYrr",
- "VMOVAPSrr",
+ "(V?)MOVAPSrr",
"VMOVDDUPYrr",
- "VMOVDDUPrr",
- "VMOVDI2PDIrr",
- "VMOVHLPSrr",
- "VMOVLHPSrr",
- "VMOVSDrr",
+ "(V?)MOVDDUPrr",
+ "(V?)MOVDI2PDIrr",
+ "(V?)MOVHLPSrr",
+ "(V?)MOVLHPSrr",
+ "(V?)MOVSDrr",
"VMOVSHDUPYrr",
- "VMOVSHDUPrr",
+ "(V?)MOVSHDUPrr",
"VMOVSLDUPYrr",
- "VMOVSLDUPrr",
- "VMOVSSrr",
+ "(V?)MOVSLDUPrr",
+ "(V?)MOVSSrr",
"VMOVUPDYrr",
- "VMOVUPDrr",
+ "(V?)MOVUPDrr",
"VMOVUPSYrr",
- "VMOVUPSrr",
+ "(V?)MOVUPSrr",
"VORPDYrr",
- "VORPDrr",
+ "(V?)ORPDrr",
"VORPSYrr",
- "VORPSrr",
+ "(V?)ORPSrr",
"VPERM2F128rr",
"VPERMILPDYri",
"VPERMILPDYrr",
@@ -379,23 +345,21 @@ def: InstRW<[SBWriteResGroup2], (instreg
"VPERMILPSri",
"VPERMILPSrr",
"VSHUFPDYrri",
- "VSHUFPDrri",
+ "(V?)SHUFPDrri",
"VSHUFPSYrri",
- "VSHUFPSrri",
+ "(V?)SHUFPSrri",
"VUNPCKHPDYrr",
- "VUNPCKHPDrr",
+ "(V?)UNPCKHPDrr",
"VUNPCKHPSYrr",
- "VUNPCKHPSrr",
+ "(V?)UNPCKHPSrr",
"VUNPCKLPDYrr",
- "VUNPCKLPDrr",
+ "(V?)UNPCKLPDrr",
"VUNPCKLPSYrr",
- "VUNPCKLPSrr",
+ "(V?)UNPCKLPSrr",
"VXORPDYrr",
- "VXORPDrr",
+ "(V?)XORPDrr",
"VXORPSYrr",
- "VXORPSrr",
- "XORPDrr",
- "XORPSrr")>;
+ "(V?)XORPSrr")>;
def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {
let Latency = 1;
@@ -409,9 +373,7 @@ def SBWriteResGroup4 : SchedWriteRes<[SB
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup4], (instregex "BLENDPDrri",
- "BLENDPSrri",
- "BT(16|32|64)ri8",
+def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr",
"BTC(16|32|64)ri8",
"BTC(16|32|64)rr",
@@ -431,9 +393,9 @@ def: InstRW<[SBWriteResGroup4], (instreg
"SHR(8|16|32|64)ri",
"SHR(8|16|32|64)r1",
"VBLENDPDYrri",
- "VBLENDPDrri",
+ "(V?)BLENDPDrri",
"VBLENDPSYrri",
- "VBLENDPSrri",
+ "(V?)BLENDPSrri",
"VMOVDQAYrr",
"VMOVDQArr",
"VMOVDQUYrr",
@@ -453,156 +415,81 @@ def: InstRW<[SBWriteResGroup5], (instreg
"MMX_PSIGNBrr",
"MMX_PSIGNDrr",
"MMX_PSIGNWrr",
- "PABSBrr",
- "PABSDrr",
- "PABSWrr",
- "PACKSSDWrr",
- "PACKSSWBrr",
- "PACKUSDWrr",
- "PACKUSWBrr",
- "PADDBrr",
- "PADDDrr",
- "PADDQrr",
- "PADDSBrr",
- "PADDSWrr",
- "PADDUSBrr",
- "PADDUSWrr",
- "PADDWrr",
- "PALIGNRrri",
- "PAVGBrr",
- "PAVGWrr",
- "PBLENDWrri",
- "PCMPEQBrr",
- "PCMPEQDrr",
- "PCMPEQQrr",
- "PCMPEQWrr",
- "PCMPGTBrr",
- "PCMPGTDrr",
- "PCMPGTWrr",
- "PMAXSBrr",
- "PMAXSDrr",
- "PMAXSWrr",
- "PMAXUBrr",
- "PMAXUDrr",
- "PMAXUWrr",
- "PMINSBrr",
- "PMINSDrr",
- "PMINSWrr",
- "PMINUBrr",
- "PMINUDrr",
- "PMINUWrr",
- "PMOVSXBDrr",
- "PMOVSXBQrr",
- "PMOVSXBWrr",
- "PMOVSXDQrr",
- "PMOVSXWDrr",
- "PMOVSXWQrr",
- "PMOVZXBDrr",
- "PMOVZXBQrr",
- "PMOVZXBWrr",
- "PMOVZXDQrr",
- "PMOVZXWDrr",
- "PMOVZXWQrr",
- "PSHUFBrr",
- "PSHUFDri",
- "PSHUFHWri",
- "PSHUFLWri",
- "PSIGNBrr",
- "PSIGNDrr",
- "PSIGNWrr",
- "PSLLDQri",
- "PSRLDQri",
- "PSUBBrr",
- "PSUBDrr",
- "PSUBQrr",
- "PSUBSBrr",
- "PSUBSWrr",
- "PSUBUSBrr",
- "PSUBUSWrr",
- "PSUBWrr",
- "PUNPCKHBWrr",
- "PUNPCKHDQrr",
- "PUNPCKHQDQrr",
- "PUNPCKHWDrr",
- "PUNPCKLBWrr",
- "PUNPCKLDQrr",
- "PUNPCKLQDQrr",
- "PUNPCKLWDrr",
- "VPABSBrr",
- "VPABSDrr",
- "VPABSWrr",
- "VPACKSSDWrr",
- "VPACKSSWBrr",
- "VPACKUSDWrr",
- "VPACKUSWBrr",
- "VPADDBrr",
- "VPADDDrr",
- "VPADDQrr",
- "VPADDSBrr",
- "VPADDSWrr",
- "VPADDUSBrr",
- "VPADDUSWrr",
- "VPADDWrr",
- "VPALIGNRrri",
- "VPAVGBrr",
- "VPAVGWrr",
- "VPBLENDWrri",
- "VPCMPEQBrr",
- "VPCMPEQDrr",
- "VPCMPEQQrr",
- "VPCMPEQWrr",
- "VPCMPGTBrr",
- "VPCMPGTDrr",
- "VPCMPGTWrr",
- "VPMAXSBrr",
- "VPMAXSDrr",
- "VPMAXSWrr",
- "VPMAXUBrr",
- "VPMAXUDrr",
- "VPMAXUWrr",
- "VPMINSBrr",
- "VPMINSDrr",
- "VPMINSWrr",
- "VPMINUBrr",
- "VPMINUDrr",
- "VPMINUWrr",
- "VPMOVSXBDrr",
- "VPMOVSXBQrr",
- "VPMOVSXBWrr",
- "VPMOVSXDQrr",
- "VPMOVSXWDrr",
- "VPMOVSXWQrr",
- "VPMOVZXBDrr",
- "VPMOVZXBQrr",
- "VPMOVZXBWrr",
- "VPMOVZXDQrr",
- "VPMOVZXWDrr",
- "VPMOVZXWQrr",
- "VPSHUFBrr",
- "VPSHUFDri",
- "VPSHUFHWri",
- "VPSHUFLWri",
- "VPSIGNBrr",
- "VPSIGNDrr",
- "VPSIGNWrr",
- "VPSLLDQri",
- "VPSRLDQri",
- "VPSUBBrr",
- "VPSUBDrr",
- "VPSUBQrr",
- "VPSUBSBrr",
- "VPSUBSWrr",
- "VPSUBUSBrr",
- "VPSUBUSWrr",
- "VPSUBWrr",
- "VPUNPCKHBWrr",
- "VPUNPCKHDQrr",
- "VPUNPCKHQDQrr",
- "VPUNPCKHWDrr",
- "VPUNPCKLBWrr",
- "VPUNPCKLDQrr",
- "VPUNPCKLQDQrr",
- "VPUNPCKLWDrr")>;
+ "(V?)PABSBrr",
+ "(V?)PABSDrr",
+ "(V?)PABSWrr",
+ "(V?)PACKSSDWrr",
+ "(V?)PACKSSWBrr",
+ "(V?)PACKUSDWrr",
+ "(V?)PACKUSWBrr",
+ "(V?)PADDBrr",
+ "(V?)PADDDrr",
+ "(V?)PADDQrr",
+ "(V?)PADDSBrr",
+ "(V?)PADDSWrr",
+ "(V?)PADDUSBrr",
+ "(V?)PADDUSWrr",
+ "(V?)PADDWrr",
+ "(V?)PALIGNRrri",
+ "(V?)PAVGBrr",
+ "(V?)PAVGWrr",
+ "(V?)PBLENDWrri",
+ "(V?)PCMPEQBrr",
+ "(V?)PCMPEQDrr",
+ "(V?)PCMPEQQrr",
+ "(V?)PCMPEQWrr",
+ "(V?)PCMPGTBrr",
+ "(V?)PCMPGTDrr",
+ "(V?)PCMPGTWrr",
+ "(V?)PMAXSBrr",
+ "(V?)PMAXSDrr",
+ "(V?)PMAXSWrr",
+ "(V?)PMAXUBrr",
+ "(V?)PMAXUDrr",
+ "(V?)PMAXUWrr",
+ "(V?)PMINSBrr",
+ "(V?)PMINSDrr",
+ "(V?)PMINSWrr",
+ "(V?)PMINUBrr",
+ "(V?)PMINUDrr",
+ "(V?)PMINUWrr",
+ "(V?)PMOVSXBDrr",
+ "(V?)PMOVSXBQrr",
+ "(V?)PMOVSXBWrr",
+ "(V?)PMOVSXDQrr",
+ "(V?)PMOVSXWDrr",
+ "(V?)PMOVSXWQrr",
+ "(V?)PMOVZXBDrr",
+ "(V?)PMOVZXBQrr",
+ "(V?)PMOVZXBWrr",
+ "(V?)PMOVZXDQrr",
+ "(V?)PMOVZXWDrr",
+ "(V?)PMOVZXWQrr",
+ "(V?)PSHUFBrr",
+ "(V?)PSHUFDri",
+ "(V?)PSHUFHWri",
+ "(V?)PSHUFLWri",
+ "(V?)PSIGNBrr",
+ "(V?)PSIGNDrr",
+ "(V?)PSIGNWrr",
+ "(V?)PSLLDQri",
+ "(V?)PSRLDQri",
+ "(V?)PSUBBrr",
+ "(V?)PSUBDrr",
+ "(V?)PSUBQrr",
+ "(V?)PSUBSBrr",
+ "(V?)PSUBSWrr",
+ "(V?)PSUBUSBrr",
+ "(V?)PSUBUSWrr",
+ "(V?)PSUBWrr",
+ "(V?)PUNPCKHBWrr",
+ "(V?)PUNPCKHDQrr",
+ "(V?)PUNPCKHQDQrr",
+ "(V?)PUNPCKHWDrr",
+ "(V?)PUNPCKLBWrr",
+ "(V?)PUNPCKLDQrr",
+ "(V?)PUNPCKLQDQrr",
+ "(V?)PUNPCKLWDrr")>;
def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
let Latency = 1;
@@ -629,7 +516,6 @@ def: InstRW<[SBWriteResGroup6], (instreg
"MOV(8|16|32|64)ri",
"MOVDQArr",
"MOVDQUrr",
- "MOVPQI2QIrr",
"MOVSX(16|32|64)rr16",
"MOVSX(16|32|64)rr32",
"MOVSX(16|32|64)rr8",
@@ -640,10 +526,6 @@ def: InstRW<[SBWriteResGroup6], (instreg
"OR(8|16|32|64)ri",
"OR(8|16|32|64)rr",
"OR(8|16|32|64)i",
- "PANDNrr",
- "PANDrr",
- "PORrr",
- "PXORrr",
"STC",
"SUB(8|16|32|64)ri",
"SUB(8|16|32|64)rr",
@@ -651,12 +533,12 @@ def: InstRW<[SBWriteResGroup6], (instreg
"TEST(8|16|32|64)rr",
"TEST(8|16|32|64)i",
"TEST(8|16|32|64)ri",
- "VMOVPQI2QIrr",
+ "(V?)MOVPQI2QIrr",
"VMOVZPQILo2PQIrr",
- "VPANDNrr",
- "VPANDrr",
- "VPORrr",
- "VPXORrr",
+ "(V?)PANDNrr",
+ "(V?)PANDrr",
+ "(V?)PORrr",
+ "(V?)PXORrr",
"XOR(8|16|32|64)ri",
"XOR(8|16|32|64)rr",
"XOR(8|16|32|64)i")>;
@@ -666,17 +548,13 @@ def SBWriteResGroup7 : SchedWriteRes<[SB
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPDrr",
- "MOVMSKPSrr",
- "MOVPDI2DIrr",
- "MOVPQIto64rr",
- "PMOVMSKBrr",
+def: InstRW<[SBWriteResGroup7], (instregex "PMOVMSKBrr",
"VMOVMSKPDYrr",
- "VMOVMSKPDrr",
+ "(V?)MOVMSKPDrr",
"VMOVMSKPSYrr",
- "VMOVMSKPSrr",
- "VMOVPDI2DIrr",
- "VMOVPQIto64rr")>;
+ "(V?)MOVMSKPSrr",
+ "(V?)MOVPDI2DIrr",
+ "(V?)MOVPQIto64rr")>;
def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> {
let Latency = 2;
@@ -728,12 +606,10 @@ def SBWriteResGroup13 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup13], (instregex "CVTPS2PDrr",
- "PTESTrr",
- "VCVTPS2PDYrr",
- "VCVTPS2PDrr",
+def: InstRW<[SBWriteResGroup13], (instregex "VCVTPS2PDYrr",
+ "(V?)CVTPS2PDrr",
"VPTESTYrr",
- "VPTESTrr")>;
+ "(V?)PTESTrr")>;
def SBWriteResGroup14 : SchedWriteRes<[SBPort0,SBPort15]> {
let Latency = 2;
@@ -769,14 +645,10 @@ def SBWriteResGroup17 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup17], (instregex "PINSRBrr",
- "PINSRDrr",
- "PINSRQrr",
- "PINSRWrr",
- "VPINSRBrr",
- "VPINSRDrr",
- "VPINSRQrr",
- "VPINSRWrr")>;
+def: InstRW<[SBWriteResGroup17], (instregex "(V?)PINSRBrr",
+ "(V?)PINSRDrr",
+ "(V?)PINSRQrr",
+ "(V?)PINSRWrr")>;
def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 2;
@@ -809,26 +681,16 @@ def SBWriteResGroup20 : SchedWriteRes<[S
def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr",
"MMX_PMULHRSWrr",
"MMX_PMULUDQirr",
- "PMADDUBSWrr",
- "PMADDWDrr",
- "PMULDQrr",
- "PMULHRSWrr",
- "PMULHUWrr",
- "PMULHWrr",
- "PMULLDrr",
- "PMULLWrr",
- "PMULUDQrr",
- "PSADBWrr",
- "VPMADDUBSWrr",
- "VPMADDWDrr",
- "VPMULDQrr",
- "VPMULHRSWrr",
- "VPMULHUWrr",
- "VPMULHWrr",
- "VPMULLDrr",
- "VPMULLWrr",
- "VPMULUDQrr",
- "VPSADBWrr")>;
+ "(V?)PMADDUBSWrr",
+ "(V?)PMADDWDrr",
+ "(V?)PMULDQrr",
+ "(V?)PMULHRSWrr",
+ "(V?)PMULHUWrr",
+ "(V?)PMULHWrr",
+ "(V?)PMULLDrr",
+ "(V?)PMULLWrr",
+ "(V?)PMULUDQrr",
+ "(V?)PSADBWrr")>;
def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
let Latency = 3;
@@ -836,99 +698,70 @@ def SBWriteResGroup21 : SchedWriteRes<[S
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup21], (instrs MUL8r, IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
-def: InstRW<[SBWriteResGroup21], (instregex "ADDPDrr",
- "ADDPSrr",
- "ADDSDrr",
- "ADDSSrr",
- "ADDSUBPDrr",
- "ADDSUBPSrr",
- "ADD_FPrST0",
+def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0",
"ADD_FST0r",
"ADD_FrST0",
"BSF(16|32|64)rr",
"BSR(16|32|64)rr",
- "CMPPDrri",
- "CMPPSrri",
- "CMPSDrr",
- "CMPSSrr",
"CRC32r(16|32|64)r8",
"CRC32r(16|32|64)r64",
- "CVTDQ2PSrr",
- "CVTPS2DQrr",
- "CVTTPS2DQrr",
- "MAX(C?)PDrr",
- "MAX(C?)PSrr",
- "MAX(C?)SDrr",
- "MAX(C?)SSrr",
- "MIN(C?)PDrr",
- "MIN(C?)PSrr",
- "MIN(C?)SDrr",
- "MIN(C?)SSrr",
"MMX_CVTPI2PSirr",
"MMX_CVTPS2PIirr",
"MMX_CVTTPS2PIirr",
"POPCNT(16|32|64)rr",
"PUSHFS64",
- "ROUNDPDr",
- "ROUNDPSr",
- "ROUNDSDr",
- "ROUNDSSr",
- "SUBPDrr",
- "SUBPSrr",
"SUBR_FPrST0",
"SUBR_FST0r",
"SUBR_FrST0",
- "SUBSDrr",
- "SUBSSrr",
"SUB_FPrST0",
"SUB_FST0r",
"SUB_FrST0",
"VADDPDYrr",
- "VADDPDrr",
+ "(V?)ADDPDrr",
"VADDPSYrr",
- "VADDPSrr",
- "VADDSDrr",
- "VADDSSrr",
+ "(V?)ADDPSrr",
+ "(V?)ADDSDrr",
+ "(V?)ADDSSrr",
"VADDSUBPDYrr",
- "VADDSUBPDrr",
+ "(V?)ADDSUBPDrr",
"VADDSUBPSYrr",
- "VADDSUBPSrr",
+ "(V?)ADDSUBPSrr",
"VCMPPDYrri",
- "VCMPPDrri",
+ "(V?)CMPPDrri",
"VCMPPSYrri",
- "VCMPPSrri",
- "VCMPSDrr",
- "VCMPSSrr",
+ "(V?)CMPPSrri",
+ "(V?)CMPSDrr",
+ "(V?)CMPSSrr",
"VCVTDQ2PSYrr",
- "VCVTDQ2PSrr",
+ "(V?)CVTDQ2PSrr",
"VCVTPS2DQYrr",
- "VCVTPS2DQrr",
+ "(V?)CVTPS2DQrr",
"VCVTTPS2DQYrr",
- "VCVTTPS2DQrr",
+ "(V?)CVTTPS2DQrr",
"VMAX(C?)PDYrr",
- "VMAX(C?)PDrr",
+ "(V?)MAX(C?)PDrr",
"VMAX(C?)PSYrr",
- "VMAX(C?)PSrr",
- "VMAX(C?)SDrr",
- "VMAX(C?)SSrr",
+ "(V?)MAX(C?)PSrr",
+ "(V?)MAX(C?)SDrr",
+ "(V?)MAX(C?)SSrr",
"VMIN(C?)PDYrr",
- "VMIN(C?)PDrr",
+ "(V?)MIN(C?)PDrr",
"VMIN(C?)PSYrr",
- "VMIN(C?)PSrr",
- "VMIN(C?)SDrr",
- "VMIN(C?)SSrr",
- "VROUNDPDr",
- "VROUNDPSr",
- "VROUNDSDr",
- "VROUNDSSr",
+ "(V?)MIN(C?)PSrr",
+ "(V?)MIN(C?)SDrr",
+ "(V?)MIN(C?)SSrr",
+ "(V?)ROUNDPDr",
+ "(V?)ROUNDPSr",
+ "(V?)ROUNDSDr",
+ "(V?)ROUNDSSr",
"VROUNDYPDr",
"VROUNDYPSr",
"VSUBPDYrr",
- "VSUBPDrr",
+ "(V?)SUBPDrr",
"VSUBPSYrr",
- "VSUBPSrr",
- "VSUBSDrr",
- "VSUBSSrr")>;
+ "(V?)SUBPSrr",
+ "(V?)SUBSDrr",
+ "(V?)SUBSSrr")>;
def SBWriteResGroup21_16i : SchedWriteRes<[SBPort1, SBPort015]> {
let Latency = 3;
@@ -949,14 +782,10 @@ def SBWriteResGroup23 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup23], (instregex "PEXTRBrr",
- "PEXTRDrr",
- "PEXTRQrr",
- "PEXTRWrr",
- "VPEXTRBrr",
- "VPEXTRDrr",
- "VPEXTRQrr",
- "VPEXTRWrr")>;
+def: InstRW<[SBWriteResGroup23], (instregex "(V?)PEXTRBrr",
+ "(V?)PEXTRDrr",
+ "(V?)PEXTRQrr",
+ "(V?)PEXTRWrr")>;
def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> {
let Latency = 3;
@@ -1038,27 +867,20 @@ def SBWriteResGroup28 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup28], (instregex "CVTDQ2PDrr",
- "CVTPD2DQrr",
- "CVTPD2PSrr",
- "CVTSD2SSrr",
- "CVTSI642SDrr",
- "CVTSI2SDrr",
- "CVTTPD2DQrr",
- "MMX_CVTPD2PIirr",
+def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPD2PIirr",
"MMX_CVTPI2PDirr",
"MMX_CVTTPD2PIirr",
"VCVTDQ2PDYrr",
- "VCVTDQ2PDrr",
+ "(V?)CVTDQ2PDrr",
"VCVTPD2DQYrr",
- "VCVTPD2DQrr",
+ "(V?)CVTPD2DQrr",
"VCVTPD2PSYrr",
- "VCVTPD2PSrr",
- "VCVTSD2SSrr",
- "VCVTSI642SDrr",
- "VCVTSI2SDrr",
+ "(V?)CVTPD2PSrr",
+ "(V?)CVTSD2SSrr",
+ "(V?)CVTSI642SDrr",
+ "(V?)CVTSI2SDrr",
"VCVTTPD2DQYrr",
- "VCVTTPD2DQrr")>;
+ "(V?)CVTTPD2DQrr")>;
def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
let Latency = 4;
@@ -1087,31 +909,21 @@ def SBWriteResGroup30 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup30], (instregex "MULPDrr",
- "MULPSrr",
- "MULSDrr",
- "MULSSrr",
- "MUL_FPrST0",
+def: InstRW<[SBWriteResGroup30], (instregex "MUL_FPrST0",
"MUL_FST0r",
"MUL_FrST0",
- "PCMPGTQrr",
- "PHMINPOSUWrr",
- "RCPPSr",
- "RCPSSr",
- "RSQRTPSr",
- "RSQRTSSr",
"VMULPDYrr",
- "VMULPDrr",
+ "(V?)MULPDrr",
"VMULPSYrr",
- "VMULPSrr",
- "VMULSDrr",
- "VMULSSrr",
- "VPCMPGTQrr",
- "VPHMINPOSUWrr",
- "VRCPPSr",
- "VRCPSSr",
- "VRSQRTPSr",
- "VRSQRTSSr")>;
+ "(V?)MULPSrr",
+ "(V?)MULSDrr",
+ "(V?)MULSSrr",
+ "(V?)PCMPGTQrr",
+ "(V?)PHMINPOSUWrr",
+ "(V?)RCPPSr",
+ "(V?)RCPSSr",
+ "(V?)RSQRTPSr",
+ "(V?)RSQRTSSr")>;
def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
let Latency = 5;
@@ -1131,22 +943,14 @@ def SBWriteResGroup32 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup32], (instregex "CVTSD2SI64rr",
- "CVTSD2SIrr",
- "CVTSS2SI64rr",
- "CVTSS2SIrr",
- "CVTTSD2SI64rr",
- "CVTTSD2SIrr",
- "CVTTSS2SI64rr",
- "CVTTSS2SIrr",
- "VCVTSD2SI64rr",
- "VCVTSD2SIrr",
- "VCVTSS2SI64rr",
- "VCVTSS2SIrr",
- "VCVTTSD2SI64rr",
- "VCVTTSD2SIrr",
- "VCVTTSS2SI64rr",
- "VCVTTSS2SIrr")>;
+def: InstRW<[SBWriteResGroup32], (instregex "(V?)CVTSD2SI64rr",
+ "(V?)CVTSD2SIrr",
+ "(V?)CVTSS2SI64rr",
+ "(V?)CVTSS2SIrr",
+ "(V?)CVTTSD2SI64rr",
+ "(V?)CVTTSD2SIrr",
+ "(V?)CVTTSS2SI64rr",
+ "(V?)CVTTSS2SIrr")>;
def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
let Latency = 5;
@@ -1154,56 +958,38 @@ def SBWriteResGroup33 : SchedWriteRes<[S
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup33], (instregex "MOV(8|16|32|64)mr",
- "MOVAPDmr",
- "MOVAPSmr",
- "MOVDQAmr",
- "MOVDQUmr",
- "MOVHPDmr",
- "MOVHPSmr",
- "MOVLPDmr",
- "MOVLPSmr",
- "MOVNTDQmr",
"MOVNTI_64mr",
"MOVNTImr",
- "MOVNTPDmr",
- "MOVNTPSmr",
- "MOVPDI2DImr",
- "MOVPQI2QImr",
- "MOVPQIto64mr",
- "MOVSDmr",
- "MOVSSmr",
- "MOVUPDmr",
- "MOVUPSmr",
"PUSH64i8",
"PUSH(16|32|64)r",
"VEXTRACTF128mr",
"VMOVAPDYmr",
- "VMOVAPDmr",
+ "(V?)MOVAPDmr",
"VMOVAPSYmr",
- "VMOVAPSmr",
+ "(V?)MOVAPSmr",
"VMOVDQAYmr",
- "VMOVDQAmr",
+ "(V?)MOVDQAmr",
"VMOVDQUYmr",
- "VMOVDQUmr",
- "VMOVHPDmr",
- "VMOVHPSmr",
- "VMOVLPDmr",
- "VMOVLPSmr",
+ "(V?)MOVDQUmr",
+ "(V?)MOVHPDmr",
+ "(V?)MOVHPSmr",
+ "(V?)MOVLPDmr",
+ "(V?)MOVLPSmr",
"VMOVNTDQYmr",
- "VMOVNTDQmr",
+ "(V?)MOVNTDQmr",
"VMOVNTPDYmr",
- "VMOVNTPDmr",
+ "(V?)MOVNTPDmr",
"VMOVNTPSYmr",
- "VMOVNTPSmr",
- "VMOVPDI2DImr",
- "VMOVPQI2QImr",
- "VMOVPQIto64mr",
- "VMOVSDmr",
- "VMOVSSmr",
+ "(V?)MOVNTPSmr",
+ "(V?)MOVPDI2DImr",
+ "(V?)MOVPQI2QImr",
+ "(V?)MOVPQIto64mr",
+ "(V?)MOVSDmr",
+ "(V?)MOVSSmr",
"VMOVUPDYmr",
- "VMOVUPDmr",
+ "(V?)MOVUPDmr",
"VMOVUPSYmr",
- "VMOVUPSmr")>;
+ "(V?)MOVUPSmr")>;
def SBWriteResGroup34 : SchedWriteRes<[SBPort0,SBPort15]> {
let Latency = 5;
@@ -1218,22 +1004,16 @@ def SBWriteResGroup35 : SchedWriteRes<[S
let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup35], (instregex "CLI")>;
-def: InstRW<[SBWriteResGroup35], (instregex "CVTSI642SSrr",
- "CVTSI2SSrr",
- "HADDPDrr",
- "HADDPSrr",
- "HSUBPDrr",
- "HSUBPSrr",
- "VCVTSI642SSrr",
- "VCVTSI2SSrr",
+def: InstRW<[SBWriteResGroup35], (instregex "(V?)CVTSI642SSrr",
+ "(V?)CVTSI2SSrr",
"VHADDPDYrr",
- "VHADDPDrr",
+ "(V?)HADDPDrr",
"VHADDPSYrr",
- "VHADDPSrr",
+ "(V?)HADDPSrr",
"VHSUBPDYrr",
- "VHSUBPDrr",
+ "(V?)HSUBPDrr",
"VHSUBPSYrr",
- "VHSUBPSrr")>;
+ "(V?)HSUBPSrr")>;
def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let Latency = 5;
@@ -1252,8 +1032,7 @@ def SBWriteResGroup36 : SchedWriteRes<[S
}
def: InstRW<[SBWriteResGroup36], (instregex "CALL64pcrel32",
"CALL(16|32|64)r",
- "EXTRACTPSmr",
- "VEXTRACTPSmr")>;
+ "(V?)EXTRACTPSmr")>;
def SBWriteResGroup37 : SchedWriteRes<[SBPort4,SBPort01,SBPort23]> {
let Latency = 5;
@@ -1277,8 +1056,7 @@ def SBWriteResGroup39 : SchedWriteRes<[S
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SBWriteResGroup39], (instregex "PEXTRBmr",
- "VPEXTRBmr",
+def: InstRW<[SBWriteResGroup39], (instregex "(V?)PEXTRBmr",
"VPEXTRDmr",
"VPEXTRWmr")>;
@@ -1319,10 +1097,8 @@ def SBWriteResGroup44 : SchedWriteRes<[S
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[SBWriteResGroup44], (instregex "LDMXCSR",
- "STMXCSR",
- "VLDMXCSR",
- "VSTMXCSR")>;
+def: InstRW<[SBWriteResGroup44], (instregex "(V?)LDMXCSR",
+ "(V?)STMXCSR")>;
def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
let Latency = 5;
@@ -1330,8 +1106,7 @@ def SBWriteResGroup45 : SchedWriteRes<[S
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SBWriteResGroup45], (instregex "PEXTRDmr",
- "PEXTRQmr",
- "VPEXTRQmr",
+ "(V?)PEXTRQmr",
"PUSHF16",
"PUSHF64")>;
@@ -1354,42 +1129,26 @@ def SBWriteResGroup48 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup48], (instregex "LDDQUrm",
- "MMX_MOVD64from64rm",
- "MOV64toPQIrm",
- "MOVAPDrm",
- "MOVAPSrm",
- "MOVDDUPrm",
- "MOVDI2PDIrm",
- "MOVDQArm",
- "MOVDQUrm",
- "MOVNTDQArm",
- "MOVQI2PQIrm",
- "MOVSDrm",
- "MOVSHDUPrm",
- "MOVSLDUPrm",
- "MOVSSrm",
- "MOVUPDrm",
- "MOVUPSrm",
+def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm",
"POP(16|32|64)r",
"VBROADCASTSSrm",
"VLDDQUYrm",
- "VLDDQUrm",
- "VMOV64toPQIrm",
- "VMOVAPDrm",
- "VMOVAPSrm",
- "VMOVDDUPrm",
- "VMOVDI2PDIrm",
- "VMOVDQArm",
- "VMOVDQUrm",
- "VMOVNTDQArm",
- "VMOVQI2PQIrm",
- "VMOVSDrm",
- "VMOVSHDUPrm",
- "VMOVSLDUPrm",
- "VMOVSSrm",
- "VMOVUPDrm",
- "VMOVUPSrm")>;
+ "(V?)LDDQUrm",
+ "(V?)MOV64toPQIrm",
+ "(V?)MOVAPDrm",
+ "(V?)MOVAPSrm",
+ "(V?)MOVDDUPrm",
+ "(V?)MOVDI2PDIrm",
+ "(V?)MOVDQArm",
+ "(V?)MOVDQUrm",
+ "(V?)MOVNTDQArm",
+ "(V?)MOVQI2PQIrm",
+ "(V?)MOVSDrm",
+ "(V?)MOVSHDUPrm",
+ "(V?)MOVSLDUPrm",
+ "(V?)MOVSSrm",
+ "(V?)MOVUPDrm",
+ "(V?)MOVUPSrm")>;
def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
let Latency = 6;
@@ -1912,98 +1671,57 @@ def SBWriteResGroup89 : SchedWriteRes<[S
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup89], (instregex "MMX_PMULUDQirm",
- "PMADDUBSWrm",
- "PMADDWDrm",
- "PMULDQrm",
- "PMULHRSWrm",
- "PMULHUWrm",
- "PMULHWrm",
- "PMULLDrm",
- "PMULLWrm",
- "PMULUDQrm",
- "PSADBWrm",
- "VPMADDUBSWrm",
- "VPMADDWDrm",
- "VPMULDQrm",
- "VPMULHRSWrm",
- "VPMULHUWrm",
- "VPMULHWrm",
- "VPMULLDrm",
- "VPMULLWrm",
- "VPMULUDQrm",
- "VPSADBWrm")>;
+ "(V?)PMADDUBSWrm",
+ "(V?)PMADDWDrm",
+ "(V?)PMULDQrm",
+ "(V?)PMULHRSWrm",
+ "(V?)PMULHUWrm",
+ "(V?)PMULHWrm",
+ "(V?)PMULLDrm",
+ "(V?)PMULLWrm",
+ "(V?)PMULUDQrm",
+ "(V?)PSADBWrm")>;
def SBWriteResGroup90 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 9;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup90], (instregex "ADDPDrm",
- "ADDPSrm",
- "ADDSDrm",
- "ADDSSrm",
- "ADDSUBPDrm",
- "ADDSUBPSrm",
- "CMPPDrmi",
- "CMPPSrmi",
- "CMPSDrm",
- "CMPSSrm",
- "CVTDQ2PSrm",
- "CVTPS2DQrm",
- "CVTSI642SDrm",
- "CVTSI2SDrm",
- "CVTTPS2DQrm",
- "MAX(C?)PDrm",
- "MAX(C?)PSrm",
- "MAX(C?)SDrm",
- "MAX(C?)SSrm",
- "MIN(C?)PDrm",
- "MIN(C?)PSrm",
- "MIN(C?)SDrm",
- "MIN(C?)SSrm",
- "MMX_CVTPI2PSirm",
+def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPI2PSirm",
"MMX_CVTPS2PIirm",
"MMX_CVTTPS2PIirm",
"POPCNT(16|32|64)rm",
- "ROUNDPDm",
- "ROUNDPSm",
- "ROUNDSDm",
- "ROUNDSSm",
- "SUBPDrm",
- "SUBPSrm",
- "SUBSDrm",
- "SUBSSrm",
- "VADDPDrm",
- "VADDPSrm",
- "VADDSDrm",
- "VADDSSrm",
- "VADDSUBPDrm",
- "VADDSUBPSrm",
- "VCMPPDrmi",
- "VCMPPSrmi",
- "VCMPSDrm",
- "VCMPSSrm",
- "VCVTDQ2PSrm",
- "VCVTPS2DQrm",
- "VCVTSI642SDrm",
- "VCVTSI2SDrm",
- "VCVTTPS2DQrm",
- "VMAX(C?)PDrm",
- "VMAX(C?)PSrm",
- "VMAX(C?)SDrm",
- "VMAX(C?)SSrm",
- "VMIN(C?)PDrm",
- "VMIN(C?)PSrm",
- "VMIN(C?)SDrm",
- "VMIN(C?)SSrm",
- "VROUNDPDm",
- "VROUNDPSm",
- "VROUNDSDm",
- "VROUNDSSm",
- "VSUBPDrm",
- "VSUBPSrm",
- "VSUBSDrm",
- "VSUBSSrm")>;
+ "(V?)ADDPDrm",
+ "(V?)ADDPSrm",
+ "(V?)ADDSDrm",
+ "(V?)ADDSSrm",
+ "(V?)ADDSUBPDrm",
+ "(V?)ADDSUBPSrm",
+ "(V?)CMPPDrmi",
+ "(V?)CMPPSrmi",
+ "(V?)CMPSDrm",
+ "(V?)CMPSSrm",
+ "(V?)CVTDQ2PSrm",
+ "(V?)CVTPS2DQrm",
+ "(V?)CVTSI642SDrm",
+ "(V?)CVTSI2SDrm",
+ "(V?)CVTTPS2DQrm",
+ "(V?)MAX(C?)PDrm",
+ "(V?)MAX(C?)PSrm",
+ "(V?)MAX(C?)SDrm",
+ "(V?)MAX(C?)SSrm",
+ "(V?)MIN(C?)PDrm",
+ "(V?)MIN(C?)PSrm",
+ "(V?)MIN(C?)SDrm",
+ "(V?)MIN(C?)SSrm",
+ "(V?)ROUNDPDm",
+ "(V?)ROUNDPSm",
+ "(V?)ROUNDSDm",
+ "(V?)ROUNDSSm",
+ "(V?)SUBPDrm",
+ "(V?)SUBPSrm",
+ "(V?)SUBSDrm",
+ "(V?)SUBSSrm")>;
def SBWriteResGroup91 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 9;
@@ -2164,24 +1882,17 @@ def SBWriteResGroup103 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SBWriteResGroup103], (instregex "CVTDQ2PDrm",
- "CVTPD2DQrm",
- "CVTPD2PSrm",
- "CVTSD2SSrm",
- "CVTSI642SSrm",
- "CVTSI2SSrm",
- "CVTTPD2DQrm",
- "MMX_CVTPD2PIirm",
+def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPD2PIirm",
"MMX_CVTPI2PDirm",
"MMX_CVTTPD2PIirm",
"VCVTDQ2PDYrm",
- "VCVTDQ2PDrm",
- "VCVTPD2DQrm",
- "VCVTPD2PSrm",
- "VCVTSD2SSrm",
- "VCVTSI642SSrm",
- "VCVTSI2SSrm",
- "VCVTTPD2DQrm")>;
+ "(V?)CVTDQ2PDrm",
+ "(V?)CVTPD2DQrm",
+ "(V?)CVTPD2PSrm",
+ "(V?)CVTSD2SSrm",
+ "(V?)CVTSI642SSrm",
+ "(V?)CVTSI2SSrm",
+ "(V?)CVTTPD2DQrm")>;
def SBWriteResGroup103_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
let Latency = 10;
@@ -2196,26 +1907,16 @@ def SBWriteResGroup104 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup104], (instregex "MULPDrm",
- "MULPSrm",
- "MULSDrm",
- "MULSSrm",
- "PCMPGTQrm",
- "PHMINPOSUWrm",
- "RCPPSm",
- "RCPSSm",
- "RSQRTPSm",
- "RSQRTSSm",
- "VMULPDrm",
- "VMULPSrm",
- "VMULSDrm",
- "VMULSSrm",
- "VPCMPGTQrm",
- "VPHMINPOSUWrm",
- "VRCPPSm",
- "VRCPSSm",
- "VRSQRTPSm",
- "VRSQRTSSm")>;
+def: InstRW<[SBWriteResGroup104], (instregex "(V?)MULPDrm",
+ "(V?)MULPSrm",
+ "(V?)MULSDrm",
+ "(V?)MULSSrm",
+ "(V?)PCMPGTQrm",
+ "(V?)PHMINPOSUWrm",
+ "(V?)RCPPSm",
+ "(V?)RCPSSm",
+ "(V?)RSQRTPSm",
+ "(V?)RSQRTSSm")>;
def SBWriteResGroup105 : SchedWriteRes<[SBPort0]> {
let Latency = 11;
@@ -2323,13 +2024,10 @@ def SBWriteResGroup116 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup116], (instregex "DIVPSrr",
- "DIVSSrr",
- "SQRTPSr",
- "SQRTSSr",
- "VDIVPSrr",
- "VDIVSSrr",
- "VSQRTPSr")>;
+def: InstRW<[SBWriteResGroup116], (instregex "SQRTSSr",
+ "(V?)DIVPSrr",
+ "(V?)DIVSSrr",
+ "(V?)SQRTPSr")>;
def SBWriteResGroup117 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 14;
@@ -2381,13 +2079,10 @@ def SBWriteResGroup123 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup123], (instregex "DIVPSrm",
- "DIVSSrm",
- "SQRTPSm",
- "SQRTSSm",
- "VDIVPSrm",
- "VDIVSSrm",
- "VSQRTPSm")>;
+def: InstRW<[SBWriteResGroup123], (instregex "SQRTSSm",
+ "(V?)DIVPSrm",
+ "(V?)DIVSSrm",
+ "(V?)SQRTPSm")>;
def SBWriteResGroup124 : SchedWriteRes<[SBPort0]> {
let Latency = 21;
@@ -2408,13 +2103,10 @@ def SBWriteResGroup126 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup126], (instregex "DIVPDrr",
- "DIVSDrr",
- "SQRTPDr",
- "SQRTSDr",
- "VDIVPDrr",
- "VDIVSDrr",
- "VSQRTPDr")>;
+def: InstRW<[SBWriteResGroup126], (instregex "SQRTSDr",
+ "(V?)DIVPDrr",
+ "(V?)DIVSDrr",
+ "(V?)SQRTPDr")>;
def SBWriteResGroup127 : SchedWriteRes<[SBPort0]> {
let Latency = 24;
@@ -2433,13 +2125,10 @@ def SBWriteResGroup128 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup128], (instregex "DIVPDrm",
- "DIVSDrm",
- "SQRTPDm",
- "SQRTSDm",
- "VDIVPDrm",
- "VDIVSDrm",
- "VSQRTPDm")>;
+def: InstRW<[SBWriteResGroup128], (instregex "SQRTSDm",
+ "(V?)DIVPDrm",
+ "(V?)DIVSDrm",
+ "(V?)SQRTPDm")>;
def SBWriteResGroup129 : SchedWriteRes<[SBPort0,SBPort05]> {
let Latency = 29;