[PATCH] D44687: [SchedModel] Remove instregex entries that don't match any instructions (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/ARM/ARMScheduleR52.td:228
 def : InstRW<[R52WriteLd,R52Read_ISS],
-      (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>;
+      (instregex "MOV_ga_pcrel_ldr")>;
 
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javed.absar wrote:
> Not sure why you removed 't2MOV_ga_pcrel_ldr' ? Is it repeated somewhere else ?
Searching through ARMGenInstrInfo.inc I could see MOV_ga_pcrel_ldr but not t2MOV_ga_pcrel_ldr - that was what caused the error.


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Comment at: lib/Target/ARM/ARMScheduleR52.td:287
+      "UMAAL", "t2SMLAL", "t2UMLAL",
       "t2SMLALBT", "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX",
       "t2SMLSLD", "t2SMLSLDX", "t2UMAAL")>;
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javed.absar wrote:
> t2MLALBB missing?
Yup - doesn't exist in ARMGenInstrInfo.inc


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Comment at: utils/TableGen/CodeGenSchedule.cpp:152
+        PrintFatalError(Loc, "instregex has no matches: " + Original);
+#if 0 // TODO
+      if (1 == NumMatches)
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craig.topper wrote:
> javed.absar wrote:
> > Just wondering why having 'just one match' would be a problem?
> Having just one match means you should probably be using "(instrs" instead of "(instregex". The regular expression has to get tried on every instruction name that is defined. If there's ever only going to be one match that just wastes tablegen build time.
Every regex pattern has to match against every instruction string - its quite costly - we're looking at ways to speed this up (PR35955).

 I'm not sure about enabling this - that's (a) why its currently #if'd out and (b) why I might reduce this to a warning if we keep it at all.


Repository:
  rL LLVM

https://reviews.llvm.org/D44687