[llvm] r328031 - [TableGen] Pass result of std::unique to vector::erase instead of calculating a size and calling resize.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 20 13:24:11 PDT 2018
Author: ctopper
Date: Tue Mar 20 13:24:10 2018
New Revision: 328031
URL: http://llvm.org/viewvc/llvm-project?rev=328031&view=rev
Log:
[TableGen] Pass result of std::unique to vector::erase instead of calculating a size and calling resize.
Added:
llvm/trunk/docs/X86Usage.rst
Modified:
llvm/trunk/docs/AMDGPUUsage.rst
llvm/trunk/docs/CodeGenerator.rst
llvm/trunk/docs/CompilerWriterInfo.rst
llvm/trunk/docs/index.rst
llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
Modified: llvm/trunk/docs/AMDGPUUsage.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AMDGPUUsage.rst?rev=328031&r1=328030&r2=328031&view=diff
==============================================================================
--- llvm/trunk/docs/AMDGPUUsage.rst (original)
+++ llvm/trunk/docs/AMDGPUUsage.rst Tue Mar 20 13:24:10 2018
@@ -1,4 +1,4 @@
-=============================
+============================
User Guide for AMDGPU Backend
=============================
Modified: llvm/trunk/docs/CodeGenerator.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.rst?rev=328031&r1=328030&r2=328031&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.rst (original)
+++ llvm/trunk/docs/CodeGenerator.rst Tue Mar 20 13:24:10 2018
@@ -2656,3 +2656,9 @@ The AMDGPU backend
The AMDGPU code generator lives in the ``lib/Target/AMDGPU``
directory. This code generator is capable of targeting a variety of
AMD GPU processors. Refer to :doc:`AMDGPUUsage` for more information.
+
+The X86 backend
+------------------
+
+The X86 code generator lives in the ``lib/Target/X86``
+directory. Refer to :doc:`X86Usage` for more information.
Modified: llvm/trunk/docs/CompilerWriterInfo.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CompilerWriterInfo.rst?rev=328031&r1=328030&r2=328031&view=diff
==============================================================================
--- llvm/trunk/docs/CompilerWriterInfo.rst (original)
+++ llvm/trunk/docs/CompilerWriterInfo.rst Tue Mar 20 13:24:10 2018
@@ -99,6 +99,8 @@ X86
* `X86 and X86-64 SysV psABI <https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI>`_
* `Calling conventions for different C++ compilers and operating systems <http://www.agner.org/optimize/calling_conventions.pdf>`_
+Refer to :doc:`X86Usage` for additional documentation.
+
XCore
-----
Added: llvm/trunk/docs/X86Usage.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/X86Usage.rst?rev=328031&view=auto
==============================================================================
--- llvm/trunk/docs/X86Usage.rst (added)
+++ llvm/trunk/docs/X86Usage.rst Tue Mar 20 13:24:10 2018
@@ -0,0 +1,85 @@
+=============================
+User Guide for X86 Backend
+=============================
+
+.. contents::
+ :local:
+
+Introduction
+============
+
+The X86 backend provides ISA code generation for X86 CPUs. It lives in the
+``lib/Target/X86`` directory.
+
+LLVM
+====
+
+.. _x86-processors
+
+Processors
+----------
+
+Use the ``clang -march=<Processor>`` option to specify the X86 processor.
+
+ .. table:: X86 processors
+ :name: x86-processor-table
+
+ ================== ===================
+ Processor Alternative
+ Name
+ ``i386``
+ ``i486``
+ ``i586``
+ ``pentium``
+ ``pentium-mmx``
+ ``i686``
+ ``pentiumpro``
+ ``pentium2``
+ ``pentium3`` - ``pentium3m``
+ ``pentium-m``
+ ``pentium4`` - ``pentium4m``
+ ``lakemont``
+ ``yonah``
+ ``prescott``
+ ``nocona``
+ ``core2``
+ ``penryn``
+ ``bonnell`` - ``atom``
+ ``silvermont`` - ``slm``
+ ``goldmont``
+ ``nehalem`` - ``corei7``
+ ``westmere``
+ ``sandybridge`` - ``corei7-avx``
+ ``ivybridge`` - ``core-avx-i``
+ ``haswell`` - ``core-avx2``
+ ``broadwell`` - ``skylake``
+ ``knl``
+ ``knm``
+ ``skylake-avx512`` - ``skx``
+ ``cannonlake``
+ ``icelake``
+ ``k6``
+ ``k6-2``
+ ``k6-3``
+ ``athlon`` - ``athlon-tbird``
+ ``athlon-4`` - ``athlon-xp``
+ - ``athlon-mp``
+ ``k8`` - ``opteron``
+ - ``athlon64``
+ - ``athlon-fx``
+ ``k8-sse3`` - ``opteron-sse3``
+ - ``athlon64-sse3``
+ ``amdfam10h`` - ``barcelona``
+ ``btver1``
+ ``btver2``
+ ``bdver1``
+ ``bdver2``
+ ``bdver3``
+ ``bdver4``
+ ``znver1``
+ ``geode``
+ ``winchip-c6``
+ ``winchip2``
+ ``c3``
+ ``c3-2``
+ ================== ===================
Modified: llvm/trunk/docs/index.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/index.rst?rev=328031&r1=328030&r2=328031&view=diff
==============================================================================
--- llvm/trunk/docs/index.rst (original)
+++ llvm/trunk/docs/index.rst Tue Mar 20 13:24:10 2018
@@ -276,6 +276,7 @@ For API clients and LLVM developers.
HowToUseAttributes
NVPTXUsage
AMDGPUUsage
+ X86Usage
StackMaps
InAlloca
BigEndianNEON
@@ -380,6 +381,9 @@ For API clients and LLVM developers.
:doc:`AMDGPUUsage`
This document describes using the AMDGPU backend to compile GPU kernels.
+:doc:`X86Usage`
+ This document describes using the X86 backend.
+
:doc:`StackMaps`
LLVM support for mapping instruction addresses to the location of
values and allowing code to be patched.
Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=328031&r1=328030&r2=328031&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp Tue Mar 20 13:24:10 2018
@@ -1398,8 +1398,7 @@ static void inferFromTransitions(ArrayRe
PI = I->PredTerm.begin(), PE = I->PredTerm.end(); PI != PE; ++PI) {
Preds.push_back(PI->Predicate);
}
- RecIter PredsEnd = std::unique(Preds.begin(), Preds.end());
- Preds.resize(PredsEnd - Preds.begin());
+ Preds.erase(std::unique(Preds.begin(), Preds.end()), Preds.end());
SCTrans.PredTerm = Preds;
SchedModels.getSchedClass(FromClassIdx).Transitions.push_back(SCTrans);
}
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