[PATCH] D44654: [X86][SandyBridge] SBWriteResPair +5cy and +1uop Memory Folds

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, gadi.haber, courbet.

As mentioned on https://reviews.llvm.org/D44647, this patch increases the default memory latency to +5cy as well as costing +1uop, which more closely matches what most custom cases are doing for reg-mem instructions.

I've left ReadAfterLd at 4cy at the moment, which seems to be correct for 'pure' loads - should I can increase this to 5 as well? What about WriteLoad etc?

As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests...


Repository:
  rL LLVM

https://reviews.llvm.org/D44654

Files:
  lib/Target/X86/X86SchedSandyBridge.td
  test/CodeGen/X86/3dnow-schedule.ll
  test/CodeGen/X86/adx-schedule.ll
  test/CodeGen/X86/avx-schedule.ll
  test/CodeGen/X86/avx2-schedule.ll
  test/CodeGen/X86/avx512-schedule.ll
  test/CodeGen/X86/avx512-shuffle-schedule.ll
  test/CodeGen/X86/avx512vpopcntdq-schedule.ll
  test/CodeGen/X86/bmi-schedule.ll
  test/CodeGen/X86/bmi2-schedule.ll
  test/CodeGen/X86/f16c-schedule.ll
  test/CodeGen/X86/fma-schedule.ll
  test/CodeGen/X86/fma4-schedule.ll
  test/CodeGen/X86/lzcnt-schedule.ll
  test/CodeGen/X86/mmx-schedule.ll
  test/CodeGen/X86/movbe-schedule.ll
  test/CodeGen/X86/schedule-x86_32.ll
  test/CodeGen/X86/schedule-x86_64.ll
  test/CodeGen/X86/sha-schedule.ll
  test/CodeGen/X86/sse2-schedule.ll
  test/CodeGen/X86/sse41-schedule.ll
  test/CodeGen/X86/sse42-schedule.ll
  test/CodeGen/X86/tbm-schedule.ll
  test/CodeGen/X86/x87-schedule.ll
  test/CodeGen/X86/xop-schedule.ll