[llvm] r327889 - [Power9]Legalize and emit code for quad-precision copySign/abs/nabs/neg/sqrt
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 19 12:22:52 PDT 2018
Author: lei
Date: Mon Mar 19 12:22:52 2018
New Revision: 327889
URL: http://llvm.org/viewvc/llvm-project?rev=327889&view=rev
Log:
[Power9]Legalize and emit code for quad-precision copySign/abs/nabs/neg/sqrt
Legalize and emit code for quad-precision floating point operations:
* xscpsgnqp
* xsabsqp
* xsnabsqp
* xsnegqp
* xssqrtqp
Differential Revision: https://reviews.llvm.org/D44530
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=327889&r1=327888&r2=327889&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Mon Mar 19 12:22:52 2018
@@ -2386,12 +2386,17 @@ let AddedComplexity = 400, Predicates =
// Quad-Precision Scalar Move Instructions:
// Copy Sign
- def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp", []>;
+ def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp",
+ [(set f128:$vT,
+ (fcopysign f128:$vB, f128:$vA))]>;
// Absolute/Negative-Absolute/Negate
- def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp" , []>;
- def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp", []>;
- def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp" , []>;
+ def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp",
+ [(set f128:$vT, (fabs f128:$vB))]>;
+ def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp",
+ [(set f128:$vT, (fneg (fabs f128:$vB)))]>;
+ def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp",
+ [(set f128:$vT, (fneg f128:$vB))]>;
//===--------------------------------------------------------------------===//
// Quad-Precision Scalar Floating-Point Arithmetic Instructions:
@@ -2414,7 +2419,8 @@ let AddedComplexity = 400, Predicates =
def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo", []>;
// Square-Root
- def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp" , []>;
+ def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp",
+ [(set f128:$vT, (fsqrt f128:$vB))]>;
def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo", []>;
// (Negative) Multiply-{Add/Subtract}
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll?rev=327889&r1=327888&r2=327889&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll Mon Mar 19 12:22:52 2018
@@ -71,3 +71,79 @@ entry:
; CHECK stxvx
; CHECK-NEXT blr
}
+
+define void @qpSqrt(fp128* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %1 = tail call fp128 @llvm.sqrt.f128(fp128 %0)
+ store fp128 %1, fp128* %res, align 16
+ ret void
+
+; CHECK-LABEL: qpSqrt
+; CHECK-NOT bl sqrtl
+; CHECK xssqrtqp
+; CHECK stxv
+; CHECK blr
+}
+declare fp128 @llvm.sqrt.f128(fp128 %Val)
+
+define void @qpCpsgn(fp128* nocapture readonly %a, fp128* nocapture readonly %b,
+ fp128* nocapture %res) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %1 = load fp128, fp128* %b, align 16
+ %2 = tail call fp128 @llvm.copysign.f128(fp128 %0, fp128 %1)
+ store fp128 %2, fp128* %res, align 16
+ ret void
+
+; CHECK-LABEL: qpSqrt
+; CHECK-NOT rldimi
+; CHECK xscpsgnqp
+; CHECK stxv
+; CHECK blr
+}
+declare fp128 @llvm.copysign.f128(fp128 %Mag, fp128 %Sgn)
+
+define void @qpAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
+ store fp128 %1, fp128* %res, align 16
+ ret void
+
+; CHECK-LABEL: qpAbs
+; CHECK-NOT clrldi
+; CHECK xsabsqp
+; CHECK stxv
+; CHECK blr
+}
+declare fp128 @llvm.fabs.f128(fp128 %Val)
+
+define void @qpNAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
+ %neg = fsub fp128 0xL00000000000000008000000000000000, %1
+ store fp128 %neg, fp128* %res, align 16
+ ret void
+
+; CHECK-LABEL: qpNAbs
+; CHECK-NOT bl __subtf3
+; CHECK xsnabsqp
+; CHECK stxv
+; CHECK blr
+}
+
+define void @qpNeg(fp128* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %sub = fsub fp128 0xL00000000000000008000000000000000, %0
+ store fp128 %sub, fp128* %res, align 16
+ ret void
+
+; CHECK-LABEL: qpNeg
+; CHECK-NOT bl __subtf3
+; CHECK xsnegqp
+; CHECK stxv
+; CHECK blr
+}
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