[llvm] r327886 - [llvm-mca] Simplify code. NFC
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 19 12:09:38 PDT 2018
Author: adibiagio
Date: Mon Mar 19 12:09:38 2018
New Revision: 327886
URL: http://llvm.org/viewvc/llvm-project?rev=327886&view=rev
Log:
[llvm-mca] Simplify code. NFC
Modified:
llvm/trunk/tools/llvm-mca/Dispatch.cpp
llvm/trunk/tools/llvm-mca/Scheduler.cpp
llvm/trunk/tools/llvm-mca/Scheduler.h
Modified: llvm/trunk/tools/llvm-mca/Dispatch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Dispatch.cpp?rev=327886&r1=327885&r2=327886&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Dispatch.cpp (original)
+++ llvm/trunk/tools/llvm-mca/Dispatch.cpp Mon Mar 19 12:09:38 2018
@@ -385,7 +385,7 @@ unsigned DispatchUnit::dispatch(unsigned
NewInst->setRCUTokenID(RCUTokenID);
notifyInstructionDispatched(IID);
- SC->scheduleInstruction(IID, NewInst);
+ SC->scheduleInstruction(IID, *NewInst);
return RCUTokenID;
}
Modified: llvm/trunk/tools/llvm-mca/Scheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Scheduler.cpp?rev=327886&r1=327885&r2=327886&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Scheduler.cpp (original)
+++ llvm/trunk/tools/llvm-mca/Scheduler.cpp Mon Mar 19 12:09:38 2018
@@ -146,9 +146,20 @@ void ResourceManager::release(ResourceRe
}
}
-void ResourceManager::reserveDispatchHazardResources(
- const ArrayRef<uint64_t> Buffers) {
+ResourceStateEvent
+ResourceManager::canBeDispatched(const ArrayRef<uint64_t> Buffers) const {
+ ResourceStateEvent Result = ResourceStateEvent::RS_BUFFER_AVAILABLE;
+ for (uint64_t Buffer : Buffers) {
+ Result = isBufferAvailable(Buffer);
+ if (Result != ResourceStateEvent::RS_BUFFER_AVAILABLE)
+ break;
+ }
+ return Result;
+}
+
+void ResourceManager::reserveBuffers(const ArrayRef<uint64_t> Buffers) {
for (const uint64_t R : Buffers) {
+ reserveBuffer(R);
ResourceState &Resource = *Resources[R];
if (Resource.isADispatchHazard()) {
assert(!Resource.isReserved());
@@ -157,6 +168,11 @@ void ResourceManager::reserveDispatchHaz
}
}
+void ResourceManager::releaseBuffers(const ArrayRef<uint64_t> Buffers) {
+ for (const uint64_t R : Buffers)
+ releaseBuffer(R);
+}
+
bool ResourceManager::canBeIssued(const InstrDesc &Desc) const {
return std::all_of(Desc.Resources.begin(), Desc.Resources.end(),
[&](const std::pair<uint64_t, const ResourceUsage> &E) {
@@ -235,7 +251,7 @@ void ResourceManager::cycleEvent(SmallVe
BusyResources.erase(RF);
}
-Instruction *Scheduler::scheduleInstruction(unsigned Idx, Instruction *MCIS) {
+void Scheduler::scheduleInstruction(unsigned Idx, Instruction &MCIS) {
assert(WaitQueue.find(Idx) == WaitQueue.end());
assert(ReadyQueue.find(Idx) == ReadyQueue.end());
assert(IssuedQueue.find(Idx) == IssuedQueue.end());
@@ -248,37 +264,37 @@ Instruction *Scheduler::scheduleInstruct
// Zero-idiom instruction (for example: a `xor reg, reg`) can also be
// eliminated at register renaming stage, since we know in advance that those
// clear their output register.
- if (MCIS->isZeroLatency()) {
+ if (MCIS.isZeroLatency()) {
notifyInstructionReady(Idx);
- MCIS->forceExecuted();
+ MCIS.forceExecuted();
notifyInstructionIssued(Idx, {});
notifyInstructionExecuted(Idx);
- return MCIS;
+ return;
}
// Consume entries in the reservation stations.
- const InstrDesc &Desc = MCIS->getDesc();
- Resources->reserveBuffers(Desc.Buffers);
+ const InstrDesc &Desc = MCIS.getDesc();
- // Mark units with BufferSize=0 as reserved. These resources will only
- // be released after MCIS is issued, and all the ResourceCycles for
- // those units have been consumed.
- Resources->reserveDispatchHazardResources(Desc.Buffers);
+ // Reserve a slot in each buffered resource. Also, mark units with
+ // BufferSize=0 as reserved. Resources with a buffer size of zero will only be
+ // released after MCIS is issued, and all the ResourceCycles for those units
+ // have been consumed.
+ Resources->reserveBuffers(Desc.Buffers);
bool MayLoad = Desc.MayLoad;
bool MayStore = Desc.MayStore;
if (MayLoad || MayStore)
LSU->reserve(Idx, MayLoad, MayStore, Desc.HasSideEffects);
- MCIS->dispatch();
- bool IsReady = MCIS->isReady();
+ MCIS.dispatch();
+ bool IsReady = MCIS.isReady();
if (IsReady && (MayLoad || MayStore))
IsReady &= LSU->isReady(Idx);
if (!IsReady) {
DEBUG(dbgs() << "[SCHEDULER] Adding " << Idx << " to the Wait Queue\n");
- WaitQueue[Idx] = MCIS;
- return MCIS;
+ WaitQueue[Idx] = &MCIS;
+ return;
}
notifyInstructionReady(Idx);
@@ -289,13 +305,11 @@ Instruction *Scheduler::scheduleInstruct
if (Resources->mustIssueImmediately(Desc)) {
DEBUG(dbgs() << "[SCHEDULER] Instruction " << Idx
<< " issued immediately\n");
- issueInstruction(MCIS, Idx);
- return MCIS;
+ return issueInstruction(MCIS, Idx);
}
DEBUG(dbgs() << "[SCHEDULER] Adding " << Idx << " to the Ready Queue\n");
- ReadyQueue[Idx] = MCIS;
- return MCIS;
+ ReadyQueue[Idx] = &MCIS;
}
void Scheduler::cycleEvent(unsigned /* unused */) {
@@ -339,7 +353,7 @@ Scheduler::Event Scheduler::canBeDispatc
return Event;
}
-void Scheduler::issueInstruction(Instruction *IS, unsigned InstrIndex) {
+void Scheduler::issueInstruction(Instruction &IS, unsigned InstrIndex) {
// Issue the instruction and collect all the consumed resources
// into a vector. That vector is then used to notify the listener.
// Most instructions consume very few resurces (typically one or
@@ -348,14 +362,14 @@ void Scheduler::issueInstruction(Instruc
// the cases.
SmallVector<std::pair<ResourceRef, unsigned>, 4> UsedResources;
- const InstrDesc &D = IS->getDesc();
+ const InstrDesc &D = IS.getDesc();
Resources->issueInstruction(InstrIndex, D, UsedResources);
// Notify the instruction that it started executing.
// This updates the internal state of each write.
- IS->execute();
+ IS.execute();
if (D.MaxLatency) {
- IssuedQueue[InstrIndex] = IS;
+ IssuedQueue[InstrIndex] = &IS;
notifyInstructionIssued(InstrIndex, UsedResources);
} else {
// A zero latency instruction which reads and/or updates registers.
@@ -369,8 +383,8 @@ void Scheduler::issue() {
for (const QueueEntryTy QueueEntry : ReadyQueue) {
// Give priority to older instructions in ReadyQueue. The ready queue is
// ordered by key, and therefore older instructions are visited first.
- Instruction *IS = QueueEntry.second;
- const InstrDesc &D = IS->getDesc();
+ Instruction &IS = *QueueEntry.second;
+ const InstrDesc &D = IS.getDesc();
if (!Resources->canBeIssued(D))
continue;
unsigned InstrIndex = QueueEntry.first;
Modified: llvm/trunk/tools/llvm-mca/Scheduler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Scheduler.h?rev=327886&r1=327885&r2=327886&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Scheduler.h (original)
+++ llvm/trunk/tools/llvm-mca/Scheduler.h Mon Mar 19 12:09:38 2018
@@ -356,27 +356,17 @@ class ResourceManager {
public:
ResourceManager(const llvm::MCSchedModel &SM) { initialize(SM); }
+ // Returns RS_BUFFER_AVAILABLE if buffered resources are not reserved, and if
+ // there are enough available slots in the buffers.
ResourceStateEvent
- canBeDispatched(const llvm::ArrayRef<uint64_t> Buffers) const {
- ResourceStateEvent Result = ResourceStateEvent::RS_BUFFER_AVAILABLE;
- for (uint64_t Buffer : Buffers) {
- Result = isBufferAvailable(Buffer);
- if (Result != ResourceStateEvent::RS_BUFFER_AVAILABLE)
- break;
- }
-
- return Result;
- }
+ canBeDispatched(const llvm::ArrayRef<uint64_t> Buffers) const;
- void reserveBuffers(const llvm::ArrayRef<uint64_t> Buffers) {
- for (const uint64_t R : Buffers)
- reserveBuffer(R);
- }
+ // Consume a slot in every buffered resource from array 'Buffers'. Resource
+ // units that are dispatch hazards (i.e. BufferSize=0) are marked as reserved.
+ void reserveBuffers(const llvm::ArrayRef<uint64_t> Buffers);
- void releaseBuffers(const llvm::ArrayRef<uint64_t> Buffers) {
- for (const uint64_t R : Buffers)
- releaseBuffer(R);
- }
+ // Release buffer entries previously allocated by method reserveBuffers.
+ void releaseBuffers(const llvm::ArrayRef<uint64_t> Buffers);
void reserveResource(uint64_t ResourceID) {
ResourceState &Resource = *Resources[ResourceID];
@@ -479,7 +469,7 @@ class Scheduler {
void issue();
/// Issue an instruction without updating the ready queue.
- void issueInstruction(Instruction *IS, unsigned InstrIndex);
+ void issueInstruction(Instruction &IS, unsigned InstrIndex);
void updatePendingQueue();
void updateIssuedQueue();
@@ -529,7 +519,7 @@ public:
};
Event canBeDispatched(const InstrDesc &Desc) const;
- Instruction *scheduleInstruction(unsigned Idx, Instruction *MCIS);
+ void scheduleInstruction(unsigned Idx, Instruction &MCIS);
void cycleEvent(unsigned Cycle);
@@ -545,7 +535,6 @@ public:
void dump() const;
#endif
};
-
} // Namespace mca
#endif
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