[llvm] r327853 - [x86] put nops into the WriteNop class and customize for Jaguar
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 19 07:26:50 PDT 2018
Author: spatel
Date: Mon Mar 19 07:26:50 2018
New Revision: 327853
URL: http://llvm.org/viewvc/llvm-project?rev=327853&view=rev
Log:
[x86] put nops into the WriteNop class and customize for Jaguar
1. Given that we already have a classification bucket with 'nop' in the name,
that's where 'nop' belongs. Right now, it's only used for prefix bytes and 'pause'.
2. Make the latency of this class '1' for Jaguar to tell the scheduler (and presumably
llvm-mca) how to model the resource requirements better even though a nop has no
dependencies.
Differential Revision: https://reviews.llvm.org/D44608
Modified:
llvm/trunk/lib/Target/X86/X86InstrFPStack.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
llvm/trunk/test/CodeGen/X86/sse-schedule.ll
llvm/trunk/test/CodeGen/X86/x87-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=327853&r1=327852&r2=327853&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Mon Mar 19 07:26:50 2018
@@ -667,10 +667,10 @@ def FNCLEX : I<0xDB, MRM_E2, (outs), (in
} // Defs = [FPSW]
} // SchedRW
-// Operandless floating-point instructions for the disassembler.
-let SchedRW = [WriteMicrocoded] in {
-def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>;
+// Operand-less floating-point instructions for the disassembler.
+def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>, Sched<[WriteNop]>;
+let SchedRW = [WriteMicrocoded] in {
let Defs = [FPSW] in {
def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>;
def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=327853&r1=327852&r2=327853&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Mar 19 07:26:50 2018
@@ -1133,7 +1133,7 @@ def trunc_su : PatFrag<(ops node:$src),
//
// Nop
-let hasSideEffects = 0, SchedRW = [WriteZero] in {
+let hasSideEffects = 0, SchedRW = [WriteNop] in {
def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
"nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=327853&r1=327852&r2=327853&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Mon Mar 19 07:26:50 2018
@@ -286,7 +286,9 @@ defm : JWriteResIntPair<WriteJump, [JAL
def : WriteRes<WriteSystem, [JALU01]> { let Latency = 100; }
def : WriteRes<WriteMicrocoded, [JALU01]> { let Latency = 100; }
def : WriteRes<WriteFence, [JSAGU]>;
-def : WriteRes<WriteNop, []>;
+// Nops don't have dependencies, so there's no actual latency, but we set this
+// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
+def : WriteRes<WriteNop, [JALU01]> { let Latency = 1; }
////////////////////////////////////////////////////////////////////////////////
// Floating point. This covers both scalar and vector operations.
Modified: llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll?rev=327853&r1=327852&r2=327853&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll Mon Mar 19 07:26:50 2018
@@ -8389,13 +8389,13 @@ define void @test_nop(i16 %a0, i32 %a1,
; BTVER2-LABEL: test_nop:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: nop # sched: [1:?]
-; BTVER2-NEXT: nopw %di # sched: [1:?]
-; BTVER2-NEXT: nopw (%rcx) # sched: [1:?]
-; BTVER2-NEXT: nopl %esi # sched: [1:?]
-; BTVER2-NEXT: nopl (%r8) # sched: [1:?]
-; BTVER2-NEXT: nopq %rdx # sched: [1:?]
-; BTVER2-NEXT: nopq (%r9) # sched: [1:?]
+; BTVER2-NEXT: nop # sched: [1:0.50]
+; BTVER2-NEXT: nopw %di # sched: [1:0.50]
+; BTVER2-NEXT: nopw (%rcx) # sched: [1:0.50]
+; BTVER2-NEXT: nopl %esi # sched: [1:0.50]
+; BTVER2-NEXT: nopl (%r8) # sched: [1:0.50]
+; BTVER2-NEXT: nopq %rdx # sched: [1:0.50]
+; BTVER2-NEXT: nopq (%r9) # sched: [1:0.50]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -9500,7 +9500,7 @@ define void @test_pause() optsize {
; BTVER2-LABEL: test_pause:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: pause # sched: [1:?]
+; BTVER2-NEXT: pause # sched: [1:0.50]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retq # sched: [4:1.00]
;
Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=327853&r1=327852&r2=327853&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Mon Mar 19 07:26:50 2018
@@ -3763,7 +3763,7 @@ define <4 x float> @test_xorps(<4 x floa
ret <4 x float> %7
}
-; 'WriteZero' class instructions.
+; 'WriteZero' and 'WriteNop' class instructions.
define <4 x float> @test_fnop() nounwind {
; GENERIC-LABEL: test_fnop:
@@ -3840,7 +3840,7 @@ define <4 x float> @test_fnop() nounwind
; BTVER2: # %bb.0:
; BTVER2-NEXT: vxorps %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: nop # sched: [1:?]
+; BTVER2-NEXT: nop # sched: [1:0.50]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retq # sched: [4:1.00]
;
Modified: llvm/trunk/test/CodeGen/X86/x87-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x87-schedule.ll?rev=327853&r1=327852&r2=327853&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x87-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x87-schedule.ll Mon Mar 19 07:26:50 2018
@@ -3209,7 +3209,7 @@ define void @test_fnop() optsize {
; SLM-LABEL: test_fnop:
; SLM: # %bb.0:
; SLM-NEXT: #APP
-; SLM-NEXT: fnop # sched: [100:1.00]
+; SLM-NEXT: fnop # sched: [1:?]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retl # sched: [4:1.00]
;
@@ -3251,7 +3251,7 @@ define void @test_fnop() optsize {
; BTVER2-LABEL: test_fnop:
; BTVER2: # %bb.0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: fnop # sched: [100:0.50]
+; BTVER2-NEXT: fnop # sched: [1:0.50]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retl # sched: [4:1.00]
;
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