[PATCH] D44612: [X86] Generalize schedule classes to support multiple stages

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: courbet, craig.topper, gadi.haber, andreadb, spatel.

Currently the WriteResPair style muliclasses take a single pipeline stage and latency, this patch generalizes this to make it easier to use with more complex schedules with ResourceCycles and NumMicroOps to be overriden from their defaults.

This has already been done for the Jaguar scheduler to remove a number of custom schedule classes and adding it to the other x86 targets will make it much tidier as we add additional classes in the future to try and replace so many custom cases.

I've converted some instructions but a lot of the models need a bit of cleanup after the patch has been committed - memory latencies not being consistent, the class not actually being used when we could remove some/all customs, etc. I'd prefer to keep this as NFC as possible so later patches can be smaller and target specific.


Repository:
  rL LLVM

https://reviews.llvm.org/D44612

Files:
  lib/Target/X86/X86SchedBroadwell.td
  lib/Target/X86/X86SchedHaswell.td
  lib/Target/X86/X86SchedSandyBridge.td
  lib/Target/X86/X86SchedSkylakeClient.td
  lib/Target/X86/X86SchedSkylakeServer.td
  lib/Target/X86/X86ScheduleSLM.td
  lib/Target/X86/X86ScheduleZnver1.td
  test/CodeGen/X86/avx2-schedule.ll

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