[PATCH] D44608: [x86] put nops into the WriteNop class and make latency = 0 for Jaguar

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, craig.topper, courbet.
Herald added a subscriber: mcrosier.

1. Given that we already have a classification bucket with 'nop' in the name, I think that's where 'nop' belongs. Right now, it's only otherwise used for prefix bytes.
2. Make the latency of this class '0' because it has no dependencies.

I'm stopping there to make sure I'm on the right track. If so, then I can change other CPU sched models where either latency is not set to 0 for WriteNop (eg SNB) or it's explicitly overridden by instregex (eg HSW).


https://reviews.llvm.org/D44608

Files:
  lib/Target/X86/X86InstrInfo.td
  lib/Target/X86/X86ScheduleBtVer2.td
  test/CodeGen/X86/schedule-x86_64.ll
  test/CodeGen/X86/sse-schedule.ll


Index: test/CodeGen/X86/sse-schedule.ll
===================================================================
--- test/CodeGen/X86/sse-schedule.ll
+++ test/CodeGen/X86/sse-schedule.ll
@@ -3763,7 +3763,7 @@
   ret <4 x float> %7
 }
 
-; 'WriteZero' class instructions.
+; 'WriteZero' and 'WriteNop' class instructions.
 
 define <4 x float> @test_fnop() nounwind {
 ; GENERIC-LABEL: test_fnop:
@@ -3840,7 +3840,7 @@
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vxorps %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    nop # sched: [1:?]
+; BTVER2-NEXT:    nop # sched: [0:?]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
Index: test/CodeGen/X86/schedule-x86_64.ll
===================================================================
--- test/CodeGen/X86/schedule-x86_64.ll
+++ test/CodeGen/X86/schedule-x86_64.ll
@@ -8389,13 +8389,13 @@
 ; BTVER2-LABEL: test_nop:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    nop # sched: [1:?]
-; BTVER2-NEXT:    nopw %di # sched: [1:?]
-; BTVER2-NEXT:    nopw (%rcx) # sched: [1:?]
-; BTVER2-NEXT:    nopl %esi # sched: [1:?]
-; BTVER2-NEXT:    nopl (%r8) # sched: [1:?]
-; BTVER2-NEXT:    nopq %rdx # sched: [1:?]
-; BTVER2-NEXT:    nopq (%r9) # sched: [1:?]
+; BTVER2-NEXT:    nop # sched: [0:?]
+; BTVER2-NEXT:    nopw %di # sched: [0:?]
+; BTVER2-NEXT:    nopw (%rcx) # sched: [0:?]
+; BTVER2-NEXT:    nopl %esi # sched: [0:?]
+; BTVER2-NEXT:    nopl (%r8) # sched: [0:?]
+; BTVER2-NEXT:    nopq %rdx # sched: [0:?]
+; BTVER2-NEXT:    nopq (%r9) # sched: [0:?]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
@@ -9500,7 +9500,7 @@
 ; BTVER2-LABEL: test_pause:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    pause # sched: [1:?]
+; BTVER2-NEXT:    pause # sched: [0:?]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
Index: lib/Target/X86/X86ScheduleBtVer2.td
===================================================================
--- lib/Target/X86/X86ScheduleBtVer2.td
+++ lib/Target/X86/X86ScheduleBtVer2.td
@@ -271,7 +271,7 @@
 def : WriteRes<WriteSystem,     [JALU01]> { let Latency = 100; }
 def : WriteRes<WriteMicrocoded, [JALU01]> { let Latency = 100; }
 def : WriteRes<WriteFence,  [JSAGU]>;
-def : WriteRes<WriteNop, []>;
+def : WriteRes<WriteNop, []> { let Latency = 0; }
 
 ////////////////////////////////////////////////////////////////////////////////
 // Floating point. This covers both scalar and vector operations.
Index: lib/Target/X86/X86InstrInfo.td
===================================================================
--- lib/Target/X86/X86InstrInfo.td
+++ lib/Target/X86/X86InstrInfo.td
@@ -1133,7 +1133,7 @@
 //
 
 // Nop
-let hasSideEffects = 0, SchedRW = [WriteZero] in {
+let hasSideEffects = 0, SchedRW = [WriteNop] in {
   def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
   def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
                 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;


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