[llvm] r327783 - [X86] Remove MMX_MASKMOVQ64 and VMASKMOVDQU from scheduler models.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 17 20:24:42 PDT 2018
Author: ctopper
Date: Sat Mar 17 20:24:42 2018
New Revision: 327783
URL: http://llvm.org/viewvc/llvm-project?rev=327783&view=rev
Log:
[X86] Remove MMX_MASKMOVQ64 and VMASKMOVDQU from scheduler models.
The information was so wildly inaccurate and incomplete its better to just remove it.
MMX_MASKMOVQ64 showed up twice in several scheduler models. In Haswell and Broadwell they were on adjacent lines. On Skylake the copies had different information.
MMX_MASKMOVQ and MASKMOVDQU were completely missing.
MMX_MASKMOVQ64 was listed on Haswell/Broadwell as 1 cycle on port 1 despite it being a store instruction.
Filed PR36780 to track fixing this right.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=327783&r1=327782&r2=327783&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sat Mar 17 20:24:42 2018
@@ -385,11 +385,8 @@ def BWWriteResGroup2 : SchedWriteRes<[BW
}
def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r")>;
def: InstRW<[BWWriteResGroup2], (instregex "COM_FST0r")>;
-def: InstRW<[BWWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;
-def: InstRW<[BWWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;
def: InstRW<[BWWriteResGroup2], (instregex "UCOM_FPr")>;
def: InstRW<[BWWriteResGroup2], (instregex "UCOM_Fr")>;
-def: InstRW<[BWWriteResGroup2], (instregex "VMASKMOVDQU")>;
def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
let Latency = 1;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=327783&r1=327782&r2=327783&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Mar 17 20:24:42 2018
@@ -953,11 +953,8 @@ def HWWriteResGroup3 : SchedWriteRes<[HW
}
def: InstRW<[HWWriteResGroup3], (instregex "COMP_FST0r")>;
def: InstRW<[HWWriteResGroup3], (instregex "COM_FST0r")>;
-def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
-def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
def: InstRW<[HWWriteResGroup3], (instregex "UCOM_FPr")>;
def: InstRW<[HWWriteResGroup3], (instregex "UCOM_Fr")>;
-def: InstRW<[HWWriteResGroup3], (instregex "VMASKMOVDQU")>;
def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
let Latency = 1;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=327783&r1=327782&r2=327783&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Mar 17 20:24:42 2018
@@ -357,13 +357,6 @@ def: InstRW<[SKLWriteResGroup1], (instre
def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBUSBirr")>;
def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PSUBUSWirr")>;
-def SKLWriteResGroup2 : SchedWriteRes<[SKLPort1]> {
- let Latency = 1;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SKLWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;
-
def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
let Latency = 1;
let NumMicroOps = 1;
@@ -1097,8 +1090,6 @@ def SKLWriteResGroup18 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup18], (instregex "MMX_MASKMOVQ64")>;
-def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVDQU")>;
def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDYmr")>;
def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDmr")>;
def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPSYmr")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=327783&r1=327782&r2=327783&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Mar 17 20:24:42 2018
@@ -397,13 +397,6 @@ def: InstRW<[SKXWriteResGroup1], (instre
def: InstRW<[SKXWriteResGroup1], (instregex "VPMOVW2MZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup1], (instregex "VPMOVW2MZrr(b?)(k?)(z?)")>;
-def SKXWriteResGroup2 : SchedWriteRes<[SKXPort1]> {
- let Latency = 1;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SKXWriteResGroup2], (instregex "MMX_MASKMOVQ64")>;
-
def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
let Latency = 1;
let NumMicroOps = 1;
@@ -1599,8 +1592,6 @@ def SKXWriteResGroup18 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup18], (instregex "MMX_MASKMOVQ64")>;
-def: InstRW<[SKXWriteResGroup18], (instregex "VMASKMOVDQU")>;
def: InstRW<[SKXWriteResGroup18], (instregex "VMASKMOVPDYmr")>;
def: InstRW<[SKXWriteResGroup18], (instregex "VMASKMOVPDmr")>;
def: InstRW<[SKXWriteResGroup18], (instregex "VMASKMOVPSYmr")>;
Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=327783&r1=327782&r2=327783&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Sat Mar 17 20:24:42 2018
@@ -2236,12 +2236,12 @@ define void @test_maskmovdqu(<16 x i8> %
;
; SKYLAKE-LABEL: test_maskmovdqu:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [2:1.00]
+; SKYLAKE-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [1:1.00]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_maskmovdqu:
; SKX: # %bb.0:
-; SKX-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [2:1.00]
+; SKX-NEXT: vmaskmovdqu %xmm1, %xmm0 # sched: [1:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_maskmovdqu:
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