[llvm] r327779 - [AArch64] Skip an unnecessary getCopyToReg in DYNAMIC_STACKALLOC
Martin Storsjo via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 17 13:08:49 PDT 2018
Author: mstorsjo
Date: Sat Mar 17 13:08:48 2018
New Revision: 327779
URL: http://llvm.org/viewvc/llvm-project?rev=327779&view=rev
Log:
[AArch64] Skip an unnecessary getCopyToReg in DYNAMIC_STACKALLOC
Differential Revision: https://reviews.llvm.org/D44586
Modified:
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=327779&r1=327778&r2=327779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Sat Mar 17 13:08:48 2018
@@ -7527,13 +7527,10 @@ AArch64TargetLowering::LowerDYNAMIC_STAC
SDValue SP = DAG.getCopyFromReg(Chain, dl, AArch64::SP, MVT::i64);
Chain = SP.getValue(1);
SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
- Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
-
- if (Align) {
+ if (Align)
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
DAG.getConstant(-(uint64_t)Align, dl, VT));
- Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
- }
+ Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
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