[PATCH] D44573: [AArch64] Add patterns matching (fabs (fsub x y)) to (fabd x y)

[Tim Northover via Phabricator via llvm-commits]

t.p.northover added inline comments.


================
Comment at: lib/Target/AArch64/AArch64InstrInfo.td:3090-3091
 defm FABD    : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>;
+foreach VT = [ v2f32, v4f32, v2f64, v4f16, v8f16 ] in
+def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
 defm FACGE   : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",int_aarch64_neon_facge>;
----------------
The 16-bit patterns should probably be guarded by a `Requires = [HasNEON, HasFullFP16]` clause (unless TableGen has changed so `Pat` instantiations inherit Requires, which actually wouldn't be a bad idea). 


================
Comment at: lib/Target/AArch64/AArch64InstrInfo.td:3401
           (FABD64 FPR64:$Rn, FPR64:$Rm)>;
+def : Pat<(fabs (fsub f16:$Rn, f16:$Rm)), (FABD16 f16:$Rn, f16:$Rm)>;
+def : Pat<(fabs (fsub f32:$Rn, f32:$Rm)), (FABD32 f32:$Rn, f32:$Rm)>;
----------------
Similar.


Repository:
  rL LLVM

https://reviews.llvm.org/D44573