[PATCH] D44548: [DAGCombiner] Expand combining of FP logical operations to sign-setting FP operations

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: bogner, efriedma, hfinkel, craig.topper, rengolin, t.p.northover, echristo.
Herald added a subscriber: kbarton.

This patch does two things:

1. Expand the DAG combiner to handle vectors when combining FP logical ops and to produce negated absolute value
2. Enable this on PPC

I tried to split this out to two patches to handle the target independent part separately from the PPC part, however I'm not sure how to write a test case for it without a target that enables this on both scalar and vector types. I'd be happy to split it if someone has an idea on how to produce a test case.

I would appreciate it if target owners can try out this patch as it of course has the potential to cause infinite loops if they have combines that will convert `ISD::FABS` and `ISD::FNEG` into bitcasts and logical ops and their target is set to allow these combines for the respective type.


Repository:
  rL LLVM

https://reviews.llvm.org/D44548

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.h
  test/CodeGen/PowerPC/float-logic-ops.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D44548.138649.patch
Type: text/x-patch
Size: 9210 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180315/0fe9d62f/attachment.bin>