[llvm] r327662 - [AArch64] Adjust the cost model for Exynos M3

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Thu Mar 15 13:31:25 2018
New Revision: 327662

URL: http://llvm.org/viewvc/llvm-project?rev=327662&view=rev
Log:
[AArch64] Adjust the cost model for Exynos M3

Add special case for rotate right.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td?rev=327662&r1=327661&r2=327662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td Thu Mar 15 13:31:25 2018
@@ -110,6 +110,10 @@ def M3BranchLinkFastPred : SchedPredicat
                                             MI->getOperand(0).isReg() &&
                                             MI->getOperand(0).getReg() != AArch64::LR}]>;
 def M3ResetFastPred      : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
+def M3RotateFastPred     : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
+                                             MI->getOpcode() == AArch64::EXTRXrri) &&
+                                            MI->getOperand(0).isReg() && MI->getOperand(1).isReg() &&
+                                            MI->getOperand(0).getReg() == MI->getOperand(1).getReg()}]>;
 def M3ShiftLeftFastPred  : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
 
 //===----------------------------------------------------------------------===//
@@ -136,6 +140,8 @@ def M3WriteC2 : SchedWriteRes<[M3UnitC]>
 def M3WriteAX : SchedWriteVariant<[SchedVar<M3ResetFastPred,     [M3WriteZ0]>,
                                    SchedVar<M3ShiftLeftFastPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,         [M3WriteAA]>]>;
+def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotateFastPred,    [M3WriteA1]>,
+                                   SchedVar<NoSchedPred,         [M3WriteAA]>]>;
 
 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
 def M3WriteBX : SchedWriteVariant<[SchedVar<M3BranchLinkFastPred, [M3WriteAB]>,
@@ -500,6 +506,7 @@ def : InstRW<[M3WriteZ0], (instregex "^M
 // Divide and multiply instructions.
 
 // Miscellaneous instructions.
+def : InstRW<[M3WriteAY], (instregex "^EXTR[WX]rri")>;
 
 // Load instructions.
 def : InstRW<[M3WriteLD,