[PATCH] D44500: [PPC] Avoid non-simple MVT in STBRX optimization

[Guozhi Wei via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL327651: [PPC] Avoid non-simple MVT in STBRX optimization (authored by Carrot, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D44500?vs=138467&id=138587#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D44500

Files:
  llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/trunk/test/CodeGen/PowerPC/pr35402.ll


Index: llvm/trunk/test/CodeGen/PowerPC/pr35402.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr35402.ll
+++ llvm/trunk/test/CodeGen/PowerPC/pr35402.ll
@@ -0,0 +1,18 @@
+; RUN: llc -O2 < %s | FileCheck %s
+target triple = "powerpc64le-linux-gnu"
+
+define void @test(i8* %p, i64 %data) {
+entry:
+  %0 = tail call i64 @llvm.bswap.i64(i64 %data)
+  %ptr = bitcast i8* %p to i48*
+  %val = trunc i64 %0 to i48
+  store i48 %val, i48* %ptr, align 1
+  ret void
+
+; CHECK:     sth
+; CHECK:     stw
+; CHECK-NOT: stdbrx
+
+}
+
+declare i64 @llvm.bswap.i64(i64)
Index: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -12285,14 +12285,18 @@
          N->getOperand(1).getValueType() == MVT::i16 ||
          (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
           N->getOperand(1).getValueType() == MVT::i64))) {
+      // STBRX can only handle simple types.
+      EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
+      if (mVT.isExtended())
+        break;
+
       SDValue BSwapOp = N->getOperand(1).getOperand(0);
       // Do an any-extend to 32-bits if this is a half-word input.
       if (BSwapOp.getValueType() == MVT::i16)
         BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
 
       // If the type of BSWAP operand is wider than stored memory width
       // it need to be shifted to the right side before STBRX.
-      EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
       if (Op1VT.bitsGT(mVT)) {
         int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
         BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,


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