[llvm] r327640 - [llvm-mca] Simplify code. NFC.

Andrea Di Biagio via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 15 09:13:12 PDT 2018


Author: adibiagio
Date: Thu Mar 15 09:13:12 2018
New Revision: 327640

URL: http://llvm.org/viewvc/llvm-project?rev=327640&view=rev
Log:
[llvm-mca] Simplify code. NFC.

Now both method DispatchUnit::checkRAT() and DispatchUnit::canDispatch take as
input an Instruction refrence instead of an instruction descriptor.
This was requested by Simon in D44488 to simplify the diff.

Modified:
    llvm/trunk/tools/llvm-mca/Backend.cpp
    llvm/trunk/tools/llvm-mca/Dispatch.cpp
    llvm/trunk/tools/llvm-mca/Dispatch.h

Modified: llvm/trunk/tools/llvm-mca/Backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Backend.cpp?rev=327640&r1=327639&r2=327640&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Backend.cpp (original)
+++ llvm/trunk/tools/llvm-mca/Backend.cpp Thu Mar 15 09:13:12 2018
@@ -36,7 +36,7 @@ void Backend::runCycle(unsigned Cycle) {
     std::unique_ptr<Instruction> NewIS(
         IB->createInstruction(STI, IR.first, *IR.second));
     const InstrDesc &Desc = NewIS->getDesc();
-    if (!DU->isAvailable(Desc.NumMicroOps) || !DU->canDispatch(Desc))
+    if (!DU->isAvailable(Desc.NumMicroOps) || !DU->canDispatch(*NewIS))
       break;
 
     Instruction *IS = NewIS.get();

Modified: llvm/trunk/tools/llvm-mca/Dispatch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Dispatch.cpp?rev=327640&r1=327639&r2=327640&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Dispatch.cpp (original)
+++ llvm/trunk/tools/llvm-mca/Dispatch.cpp Thu Mar 15 09:13:12 2018
@@ -199,7 +199,8 @@ void RetireControlUnit::dump() const {
 }
 #endif
 
-bool DispatchUnit::checkRAT(const InstrDesc &Desc) {
+bool DispatchUnit::checkRAT(const Instruction &Instr) {
+  const InstrDesc &Desc = Instr.getDesc();
   unsigned NumWrites = Desc.Writes.size();
   if (RAT->isAvailable(NumWrites))
     return true;

Modified: llvm/trunk/tools/llvm-mca/Dispatch.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Dispatch.h?rev=327640&r1=327639&r2=327640&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Dispatch.h (original)
+++ llvm/trunk/tools/llvm-mca/Dispatch.h Thu Mar 15 09:13:12 2018
@@ -233,7 +233,7 @@ class DispatchUnit {
   // stored into a vector `DispatchStall` which is always of size DS_LAST.
   std::vector<unsigned> DispatchStalls;
 
-  bool checkRAT(const InstrDesc &Desc);
+  bool checkRAT(const Instruction &Desc);
   bool checkRCU(const InstrDesc &Desc);
   bool checkScheduler(const InstrDesc &Desc);
 
@@ -260,9 +260,10 @@ public:
 
   bool isRCUEmpty() const { return RCU->isEmpty(); }
 
-  bool canDispatch(const InstrDesc &Desc) {
+  bool canDispatch(const Instruction &Inst) {
+    const InstrDesc &Desc = Inst.getDesc();
     assert(isAvailable(Desc.NumMicroOps));
-    return checkRCU(Desc) && checkRAT(Desc) && checkScheduler(Desc);
+    return checkRCU(Desc) && checkRAT(Inst) && checkScheduler(Desc);
   }
 
   unsigned dispatch(unsigned IID, Instruction *NewInst,




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